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Add Power ISA e200 embedded core variant
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@ -23,6 +23,7 @@ data/languages/ppc_32_4xx_le.slaspec||GHIDRA||||END|
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data/languages/ppc_32_be.cspec||GHIDRA||||END|
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data/languages/ppc_32_be.slaspec||GHIDRA||||END|
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data/languages/ppc_32_be_Mac.cspec||GHIDRA||||END|
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data/languages/ppc_32_e200.slaspec||GHIDRA||||END|
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data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
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data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
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data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
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@ -8,8 +8,10 @@
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<constraint primary="497" processor="PowerPC" endian="little" size="32" />
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</constraint>
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<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
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<constraint primary="20" processor="PowerPC" size="32" />
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<constraint primary="21" processor="PowerPC" size="64" />
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<constraint primary="20" processor="PowerPC" size="32">
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<constraint secondary="0x80000000" endian="big" variant="e200" />
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</constraint>
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<constraint primary="21" processor="PowerPC" size="64" />
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</constraint>
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<constraint loader="Preferred Executable Format (PEF)" compilerSpecID="default">
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<constraint primary="pwpc" processor="PowerPC" endian="big" size="32" />
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@ -128,6 +128,21 @@
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<external_name tool="IDA-PRO" name="ppcl"/>
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<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
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</language>
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<language processor="PowerPC"
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endian="big"
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size="32"
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variant="e200"
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version="1.5"
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slafile="ppc_32_e200.sla"
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processorspec="ppc_32.pspec"
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manualindexfile="../manuals/PowerPC.idx"
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id="PowerPC:BE:32:VLE-e200">
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<description>Power ISA Embedded e200 32-bit big endian w/VLE</description>
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<compiler name="default" spec="ppc_32_be.cspec" id="default"/>
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<external_name tool="gnu" name="powerpc:e200"/>
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<external_name tool="IDA-PRO" name="ppc"/>
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<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
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</language>
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<language processor="PowerPC"
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endian="big"
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size="32"
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20
Ghidra/Processors/PowerPC/data/languages/ppc_32_e200.slaspec
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20
Ghidra/Processors/PowerPC/data/languages/ppc_32_e200.slaspec
Normal file
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@ -0,0 +1,20 @@
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# SLA specification file for the Power ISA Embedded e200 32-bit big endian core w/VLE
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@define ENDIAN "big"
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# FIXME: See note below
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# @define IS_ISA "1"
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@define REGISTER_SIZE "4"
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@define EATRUNC "ea"
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@include "ppc_common.sinc"
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@include "ppc_vle.sinc"
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# FIXME: Define IS_ISA above to bring in SPE_APU.sinc, but requires fixing
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@include "evx.sinc"
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@include "SPEF_SCR.sinc"
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# FIXME: Fix size restrictions
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# @include "SPE_EFV.sinc"
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