mirror of
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GP-4879 Initial M16C commit
This commit is contained in:
emteere
parent
403619065c
commit
c941eb027c
1
Ghidra/Processors/M16C/Module.manifest
Normal file
1
Ghidra/Processors/M16C/Module.manifest
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@ -0,0 +1 @@
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MODULE DEPENDENCY: Ghidra/Framework/SoftwareModeling
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23
Ghidra/Processors/M16C/build.gradle
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23
Ghidra/Processors/M16C/build.gradle
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@ -0,0 +1,23 @@
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/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
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apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
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apply plugin: 'eclipse'
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eclipse.project.name = 'Processors M16C'
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sleighCompileOptions = [
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'-l'
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]
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12
Ghidra/Processors/M16C/certification.manifest
Normal file
12
Ghidra/Processors/M16C/certification.manifest
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##VERSION: 2.0
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Module.manifest||GHIDRA||||END|
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data/languages/M16C_60.cspec||GHIDRA||||END|
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data/languages/M16C_60.ldefs||GHIDRA||||END|
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data/languages/M16C_60.pspec||GHIDRA||||END|
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data/languages/M16C_60.slaspec||GHIDRA||||END|
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data/languages/M16C_80.cspec||GHIDRA||||END|
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data/languages/M16C_80.ldefs||GHIDRA||||END|
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data/languages/M16C_80.pspec||GHIDRA||||END|
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data/languages/M16C_80.slaspec||GHIDRA||||END|
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data/manuals/M16C_60.idx||GHIDRA||||END|
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data/manuals/M16C_80.idx||GHIDRA||||END|
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40
Ghidra/Processors/M16C/data/languages/M16C_60.cspec
Normal file
40
Ghidra/Processors/M16C/data/languages/M16C_60.cspec
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@ -0,0 +1,40 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<global>
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<range space="RAM"/>
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</global>
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<stackpointer register="SP" space="RAM"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="unknown" stackshift="0">
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<input>
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<pentry maxsize="2" minsize="1">
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<register name="R0"/>
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</pentry>
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<pentry maxsize="2" minsize="1">
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<register name="R1"/>
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</pentry>
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<pentry maxsize="2" minsize="1">
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<register name="R2"/>
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</pentry>
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<pentry maxsize="500" minsize="1" align="2"> <!-- TODO: Alignment should be 1, waiting for decompiler change -->
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<addr space="stack" offset="0"/>
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</pentry>
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</input>
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<output>
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<pentry maxsize="2" minsize="1">
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<register name="R3"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>
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<register name="A0"/>
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<register name="A1"/>
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<register name="INTB"/>
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<register name="FB"/>
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<register name="SB"/>
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<register name="FLG"/>
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</unaffected>
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</prototype>
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</default_proto>
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</compiler_spec>
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20
Ghidra/Processors/M16C/data/languages/M16C_60.ldefs
Normal file
20
Ghidra/Processors/M16C/data/languages/M16C_60.ldefs
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<?xml version="1.0" encoding="UTF-8"?>
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<language_definitions>
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<!--
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Version-1.1 12-Dec-2008 - complete rewrite of M16C_60.slaspec
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-->
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<language processor="M16C/60"
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endian="little"
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size="16"
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variant="default"
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version="1.1"
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slafile="M16C_60.sla"
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processorspec="M16C_60.pspec"
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manualindexfile="../manuals/M16C_60.idx"
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id="M16C/60:LE:16:default">
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<description>Renesas M16C/60 16-Bit MicroComputer</description>
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<compiler name="default" spec="M16C_60.cspec" id="default"/>
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<external_name tool="gnu" name="m16c"/>
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</language>
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</language_definitions>
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169
Ghidra/Processors/M16C/data/languages/M16C_60.pspec
Normal file
169
Ghidra/Processors/M16C/data/languages/M16C_60.pspec
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@ -0,0 +1,169 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<processor_spec>
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<programcounter register="PC"/>
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<default_symbols>
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<symbol name="PM0" address="RAM:0004"/>
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<symbol name="PM1" address="RAM:0005"/>
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<symbol name="CM0" address="RAM:0006"/>
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<symbol name="CM1" address="RAM:0007"/>
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<symbol name="CSR" address="RAM:0008"/>
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<symbol name="AIER" address="RAM:0009"/>
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<symbol name="PRCR" address="RAM:000A"/>
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<symbol name="WDTS" address="RAM:000E"/>
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<symbol name="WDC" address="RAM:000F"/>
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<symbol name="RMAD0" address="RAM:0010"/>
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<symbol name="RMAD0" address="RAM:0011"/>
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<symbol name="RMAD0" address="RAM:0012"/>
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<symbol name="RMAD1" address="RAM:0014"/>
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<symbol name="RMAD1" address="RAM:0015"/>
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<symbol name="RMAD1" address="RAM:0016"/>
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<symbol name="SAR0" address="RAM:0020"/>
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<symbol name="SAR0" address="RAM:0021"/>
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<symbol name="SAR0" address="RAM:0022"/>
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<symbol name="DAR0" address="RAM:0024"/>
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<symbol name="DAR0" address="RAM:0025"/>
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<symbol name="DAR0" address="RAM:0026"/>
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<symbol name="TCR0" address="RAM:0028"/>
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<symbol name="TCR0" address="RAM:0029"/>
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<symbol name="DM0CON" address="RAM:002C"/>
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<symbol name="SAR1" address="RAM:0030"/>
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<symbol name="SAR1" address="RAM:0031"/>
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<symbol name="SAR1" address="RAM:0032"/>
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<symbol name="DAR1" address="RAM:0034"/>
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<symbol name="DAR1" address="RAM:0035"/>
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<symbol name="DAR1" address="RAM:0036"/>
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<symbol name="TCR1" address="RAM:0038"/>
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<symbol name="TCR1" address="RAM:0039"/>
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<symbol name="DM1CON" address="RAM:003C"/>
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<symbol name="DM0IC" address="RAM:004B"/>
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<symbol name="DM1IC" address="RAM:004C"/>
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<symbol name="KUPIC" address="RAM:004D"/>
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<symbol name="ADIC" address="RAM:004E"/>
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<symbol name="S0TIC" address="RAM:0051"/>
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<symbol name="S0RIC" address="RAM:0052"/>
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<symbol name="S1TIC" address="RAM:0053"/>
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<symbol name="S1RIC" address="RAM:0054"/>
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<symbol name="TA0IC" address="RAM:0055"/>
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<symbol name="TA1IC" address="RAM:0056"/>
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<symbol name="TA2IC" address="RAM:0057"/>
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<symbol name="TA3IC" address="RAM:0058"/>
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<symbol name="TA4IC" address="RAM:0059"/>
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<symbol name="TB0IC" address="RAM:005A"/>
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<symbol name="TB1IC" address="RAM:005B"/>
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<symbol name="TB2IC" address="RAM:005C"/>
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<symbol name="INT0IC" address="RAM:005D"/>
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<symbol name="INT1IC" address="RAM:005E"/>
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<symbol name="INT2IC" address="RAM:005F"/>
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<symbol name="TABSR" address="RAM:0380"/>
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<symbol name="CPSRF" address="RAM:0381"/>
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<symbol name="ONSF" address="RAM:0382"/>
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<symbol name="TRGSR" address="RAM:0383"/>
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<symbol name="UDF" address="RAM:0384"/>
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<symbol name="TA0" address="RAM:0386"/>
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<symbol name="TA0" address="RAM:0387"/>
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<symbol name="TA1" address="RAM:0388"/>
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<symbol name="TA1" address="RAM:0389"/>
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<symbol name="TA2" address="RAM:038A"/>
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<symbol name="TA2" address="RAM:038B"/>
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<symbol name="TA3" address="RAM:038C"/>
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<symbol name="TA3" address="RAM:038D"/>
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<symbol name="TA4" address="RAM:038E"/>
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<symbol name="TA4" address="RAM:038F"/>
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<symbol name="TB0" address="RAM:0390"/>
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<symbol name="TB0" address="RAM:0391"/>
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<symbol name="TB1" address="RAM:0392"/>
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<symbol name="TB1" address="RAM:0393"/>
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<symbol name="TB2" address="RAM:0394"/>
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<symbol name="TB2" address="RAM:0395"/>
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<symbol name="TA0MR" address="RAM:0396"/>
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<symbol name="TA1MR" address="RAM:0397"/>
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<symbol name="TA2MR" address="RAM:0398"/>
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<symbol name="TA3MR" address="RAM:0399"/>
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<symbol name="TA4MR" address="RAM:039A"/>
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<symbol name="TB0MR" address="RAM:039B"/>
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<symbol name="TB1MR" address="RAM:039C"/>
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<symbol name="TB2MR" address="RAM:039D"/>
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<symbol name="U0MR" address="RAM:03A0"/>
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<symbol name="U0BRG" address="RAM:03A1"/>
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<symbol name="U0TB" address="RAM:03A2"/>
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<symbol name="U0TB" address="RAM:03A3"/>
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<symbol name="U0C0" address="RAM:03A4"/>
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<symbol name="U0C1" address="RAM:03A5"/>
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<symbol name="U0RB" address="RAM:03A6"/>
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<symbol name="U0RB" address="RAM:03A7"/>
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<symbol name="U1MR" address="RAM:03A8"/>
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<symbol name="U1BRG" address="RAM:03A9"/>
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<symbol name="U1TB" address="RAM:03AA"/>
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<symbol name="U1TB" address="RAM:03AB"/>
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<symbol name="U1C0" address="RAM:03AC"/>
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<symbol name="U1C1" address="RAM:03AD"/>
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<symbol name="U1RB" address="RAM:03AE"/>
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<symbol name="U1RB" address="RAM:03AF"/>
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<symbol name="UCON" address="RAM:03B0"/>
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<symbol name="DM0SL" address="RAM:03B8"/>
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<symbol name="DM1SL" address="RAM:03BA"/>
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<symbol name="CRCD" address="RAM:03BC"/>
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<symbol name="CRCD" address="RAM:03BD"/>
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<symbol name="CRCIN" address="RAM:03BE"/>
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<symbol name="AD0" address="RAM:03C0"/>
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<symbol name="AD0" address="RAM:03C1"/>
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<symbol name="AD1" address="RAM:03C2"/>
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<symbol name="AD1" address="RAM:03C3"/>
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<symbol name="AD2" address="RAM:03C4"/>
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<symbol name="AD2" address="RAM:03C5"/>
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<symbol name="AD3" address="RAM:03C6"/>
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<symbol name="AD3" address="RAM:03C7"/>
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<symbol name="AD4" address="RAM:03C8"/>
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<symbol name="AD4" address="RAM:03C9"/>
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<symbol name="AD5" address="RAM:03CA"/>
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<symbol name="AD5" address="RAM:03CB"/>
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<symbol name="AD6" address="RAM:03CC"/>
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<symbol name="AD6" address="RAM:03CD"/>
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<symbol name="AD7" address="RAM:03CE"/>
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<symbol name="AD7" address="RAM:03CF"/>
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<symbol name="ADCON2" address="RAM:03D4"/>
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<symbol name="ADCON0" address="RAM:03D6"/>
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<symbol name="ADCON1" address="RAM:03D7"/>
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<symbol name="DA0" address="RAM:03D8"/>
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<symbol name="DA1" address="RAM:03DA"/>
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<symbol name="DACON" address="RAM:03DC"/>
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<symbol name="P0" address="RAM:03E0"/>
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<symbol name="P1" address="RAM:03E1"/>
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<symbol name="PD0" address="RAM:03E2"/>
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<symbol name="PD1" address="RAM:03E3"/>
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<symbol name="P2" address="RAM:03E4"/>
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<symbol name="P3" address="RAM:03E5"/>
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<symbol name="PD2" address="RAM:03E6"/>
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<symbol name="PD3" address="RAM:03E7"/>
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<symbol name="P4" address="RAM:03E8"/>
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<symbol name="P5" address="RAM:03E9"/>
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<symbol name="PD4" address="RAM:03EA"/>
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<symbol name="PD5" address="RAM:03EB"/>
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<symbol name="P6" address="RAM:03EC"/>
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<symbol name="P7" address="RAM:03ED"/>
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<symbol name="PD6" address="RAM:03EE"/>
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||||
<symbol name="PD7" address="RAM:03EF"/>
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<symbol name="P8" address="RAM:03F0"/>
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<symbol name="P9" address="RAM:03F1"/>
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<symbol name="PD8" address="RAM:03F2"/>
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<symbol name="PD9" address="RAM:03F3"/>
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<symbol name="P10" address="RAM:03F4"/>
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<symbol name="PD10" address="RAM:03F6"/>
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<symbol name="PUR0" address="RAM:03FC"/>
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<symbol name="PUR1" address="RAM:03FD"/>
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<symbol name="PUR2" address="RAM:03FE"/>
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<symbol name="UNDEFINED_INSTRUCTION_INT_VECTOR" address="RAM:FFFDC" entry="true" type="code_ptr"/>
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<symbol name="OVERFLOW_INT_VECTOR" address="RAM:FFFE0" entry="true" type="code_ptr"/>
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<symbol name="BRK_INSTRUCTION_INT_VECTOR" address="RAM:FFFE4" entry="true" type="code_ptr"/>
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<symbol name="ADDRESS_MATCH_INT_VECTOR" address="RAM:FFFE8" entry="true" type="code_ptr"/>
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<symbol name="SINGLE_STEP_INT_VECTOR" address="RAM:FFFEC" entry="true" type="code_ptr"/>
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<symbol name="WATCHDOG_TIMER_INT_VECTOR" address="RAM:FFFF0" entry="true" type="code_ptr"/>
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<symbol name="NOT_DBC_INT_VECTOR" address="RAM:FFFF4" entry="true" type="code_ptr"/>
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<symbol name="NOT_NMI_INT_VECTOR" address="RAM:FFFF8" entry="true" type="code_ptr"/>
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<symbol name="RESET_INT_VECTOR" address="RAM:FFFFC" entry="true" type="code_ptr"/>
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</default_symbols>
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<default_memory_blocks>
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||||
<memory_block name="SFR" start_address="RAM:0000" mode="rw" length="0x03FF" initialized="false"/>
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||||
</default_memory_blocks>
|
||||
</processor_spec>
|
||||
3627
Ghidra/Processors/M16C/data/languages/M16C_60.slaspec
Normal file
3627
Ghidra/Processors/M16C/data/languages/M16C_60.slaspec
Normal file
File diff suppressed because it is too large
Load Diff
31
Ghidra/Processors/M16C/data/languages/M16C_80.cspec
Normal file
31
Ghidra/Processors/M16C/data/languages/M16C_80.cspec
Normal file
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|
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|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<compiler_spec>
|
||||
<global>
|
||||
<range space="RAM"/>
|
||||
</global>
|
||||
<stackpointer register="SP" space="RAM"/>
|
||||
<default_proto>
|
||||
<prototype name="__stdcall" extrapop="4" stackshift="4">
|
||||
<input>
|
||||
<pentry maxsize="2" minsize="1">
|
||||
<register name="R0"/>
|
||||
</pentry>
|
||||
<pentry maxsize="500" minsize="1" align="4"> <!-- TODO: Alignment should be 2, waiting for decompiler change -->
|
||||
<addr space="stack" offset="4"/>
|
||||
</pentry>
|
||||
</input>
|
||||
<output>
|
||||
<pentry maxsize="4" minsize="1">
|
||||
<register name="R2R0"/>
|
||||
</pentry>
|
||||
</output>
|
||||
<unaffected>
|
||||
<register name="SP"/>
|
||||
<register name="FB"/>
|
||||
<register name="SB"/>
|
||||
<register name="FLG"/>
|
||||
</unaffected>
|
||||
</prototype>
|
||||
</default_proto>
|
||||
</compiler_spec>
|
||||
20
Ghidra/Processors/M16C/data/languages/M16C_80.ldefs
Normal file
20
Ghidra/Processors/M16C/data/languages/M16C_80.ldefs
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<language_definitions>
|
||||
<!--
|
||||
Version-1.1 17-Nov-2008 - complete rewrite of M16C_80.slaspec
|
||||
-->
|
||||
<language processor="M16C/80"
|
||||
endian="little"
|
||||
size="16"
|
||||
variant="default"
|
||||
version="1.1"
|
||||
slafile="M16C_80.sla"
|
||||
processorspec="M16C_80.pspec"
|
||||
manualindexfile="../manuals/M16C_80.idx"
|
||||
id="M16C/80:LE:16:default">
|
||||
<description>Renesas M16C/80 16-Bit MicroComputer</description>
|
||||
<compiler name="default" spec="M16C_80.cspec" id="default"/>
|
||||
<external_name tool="gnu" name="m16c"/>
|
||||
</language>
|
||||
</language_definitions>
|
||||
296
Ghidra/Processors/M16C/data/languages/M16C_80.pspec
Normal file
296
Ghidra/Processors/M16C/data/languages/M16C_80.pspec
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<processor_spec>
|
||||
<programcounter register="PC"/>
|
||||
<volatile outputop="write_sfr" inputop="read_sfr">
|
||||
<range space="RAM" first="0x0" last="0x03ff"/>
|
||||
</volatile>
|
||||
<default_symbols>
|
||||
<symbol name="PM0" address="RAM:0004"/>
|
||||
<symbol name="PM1" address="RAM:0005"/>
|
||||
<symbol name="CM0" address="RAM:0006"/>
|
||||
<symbol name="CM1" address="RAM:0007"/>
|
||||
<symbol name="WCR" address="RAM:0008"/>
|
||||
<symbol name="AIER" address="RAM:0009"/>
|
||||
<symbol name="PRCR" address="RAM:000A"/>
|
||||
<symbol name="DS" address="RAM:000B"/>
|
||||
<symbol name="MCD" address="RAM:000C"/>
|
||||
<symbol name="WDTS" address="RAM:000E"/>
|
||||
<symbol name="WDC" address="RAM:000F"/>
|
||||
<symbol name="RMAD0" address="RAM:0010"/>
|
||||
<symbol name="RMAD0" address="RAM:0011"/>
|
||||
<symbol name="RMAD0" address="RAM:0012"/>
|
||||
<symbol name="RMAD1" address="RAM:0014"/>
|
||||
<symbol name="RMAD1" address="RAM:0015"/>
|
||||
<symbol name="RMAD1" address="RAM:0016"/>
|
||||
<symbol name="RMAD2" address="RAM:0018"/>
|
||||
<symbol name="RMAD2" address="RAM:0019"/>
|
||||
<symbol name="RMAD2" address="RAM:001A"/>
|
||||
<symbol name="RMAD3" address="RAM:001C"/>
|
||||
<symbol name="RMAD3" address="RAM:001D"/>
|
||||
<symbol name="RMAD3" address="RAM:001E"/>
|
||||
<symbol name="EIAD" address="RAM:0020"/>
|
||||
<symbol name="EIAD" address="RAM:0021"/>
|
||||
<symbol name="EIAD" address="RAM:0022"/>
|
||||
<symbol name="EITD" address="RAM:0023"/>
|
||||
<symbol name="EPRR" address="RAM:0024"/>
|
||||
<symbol name="ROA" address="RAM:0030"/>
|
||||
<symbol name="DBA" address="RAM:0031"/>
|
||||
<symbol name="EXA0" address="RAM:0032"/>
|
||||
<symbol name="EXA1" address="RAM:0033"/>
|
||||
<symbol name="EXA2" address="RAM:0034"/>
|
||||
<symbol name="EXA3" address="RAM:0035"/>
|
||||
<symbol name="DRAMCONT" address="RAM:0040"/>
|
||||
<symbol name="REFCNT" address="RAM:0041"/>
|
||||
<symbol name="DM0IC" address="RAM:0068"/>
|
||||
<symbol name="TB5IC" address="RAM:0069"/>
|
||||
<symbol name="DM1IC" address="RAM:006A"/>
|
||||
<symbol name="S2RIC" address="RAM:006B"/>
|
||||
<symbol name="TA0IC" address="RAM:006C"/>
|
||||
<symbol name="S3RIC" address="RAM:006D"/>
|
||||
<symbol name="TA2IC" address="RAM:006E"/>
|
||||
<symbol name="SR4RIC" address="RAM:006F"/>
|
||||
<symbol name="TA4IC" address="RAM:0070"/>
|
||||
<symbol name="BCN3IC" address="RAM:0071"/>
|
||||
<symbol name="S0RIC" address="RAM:0072"/>
|
||||
<symbol name="ADIC" address="RAM:0073"/>
|
||||
<symbol name="S1RIC" address="RAM:0074"/>
|
||||
<symbol name="TB1IC" address="RAM:0076"/>
|
||||
<symbol name="TB3IC" address="RAM:0078"/>
|
||||
<symbol name="INT5IC" address="RAM:007A"/>
|
||||
<symbol name="INT3IC" address="RAM:007C"/>
|
||||
<symbol name="INT1IC" address="RAM:007E"/>
|
||||
<symbol name="DM1IC" address="RAM:0088"/>
|
||||
<symbol name="S2TIC" address="RAM:0089"/>
|
||||
<symbol name="DM3IC" address="RAM:008A"/>
|
||||
<symbol name="S3TIC" address="RAM:008B"/>
|
||||
<symbol name="TA1IC" address="RAM:008C"/>
|
||||
<symbol name="S4TIC" address="RAM:008D"/>
|
||||
<symbol name="TA3IC" address="RAM:008E"/>
|
||||
<symbol name="BCN2IC" address="RAM:008F"/>
|
||||
<symbol name="S0TIC" address="RAM:0090"/>
|
||||
<symbol name="BCN4IC" address="RAM:0091"/>
|
||||
<symbol name="S1TIC" address="RAM:0092"/>
|
||||
<symbol name="KUPIC" address="RAM:0093"/>
|
||||
<symbol name="TB0IC" address="RAM:0094"/>
|
||||
<symbol name="TB2IC" address="RAM:0096"/>
|
||||
<symbol name="TB4IC" address="RAM:0098"/>
|
||||
<symbol name="INT4IC" address="RAM:009A"/>
|
||||
<symbol name="INT2IC" address="RAM:009C"/>
|
||||
<symbol name="INT0IC" address="RAM:009E"/>
|
||||
<symbol name="RLVL" address="RAM:009F"/>
|
||||
<symbol name="Y0R" address="RAM:02C0"/>
|
||||
<symbol name="Y0R" address="RAM:02C1"/>
|
||||
<symbol name="Y1R" address="RAM:02C2"/>
|
||||
<symbol name="Y1R" address="RAM:02C3"/>
|
||||
<symbol name="Y2R" address="RAM:02C4"/>
|
||||
<symbol name="Y2R" address="RAM:02C5"/>
|
||||
<symbol name="Y3R" address="RAM:02C6"/>
|
||||
<symbol name="Y3R" address="RAM:02C7"/>
|
||||
<symbol name="Y4R" address="RAM:02C8"/>
|
||||
<symbol name="Y4R" address="RAM:02C9"/>
|
||||
<symbol name="Y5R" address="RAM:02CA"/>
|
||||
<symbol name="Y5R" address="RAM:02CB"/>
|
||||
<symbol name="Y6R" address="RAM:02CC"/>
|
||||
<symbol name="Y6R" address="RAM:02CD"/>
|
||||
<symbol name="Y7R" address="RAM:02CE"/>
|
||||
<symbol name="Y7R" address="RAM:02CF"/>
|
||||
<symbol name="Y8R" address="RAM:02D0"/>
|
||||
<symbol name="Y8R" address="RAM:02D1"/>
|
||||
<symbol name="Y9R" address="RAM:02D2"/>
|
||||
<symbol name="Y9R" address="RAM:02D3"/>
|
||||
<symbol name="Y10R" address="RAM:02D4"/>
|
||||
<symbol name="Y10R" address="RAM:02D5"/>
|
||||
<symbol name="Y11R" address="RAM:02D6"/>
|
||||
<symbol name="Y11R" address="RAM:02D7"/>
|
||||
<symbol name="Y12R" address="RAM:02D8"/>
|
||||
<symbol name="Y12R" address="RAM:02D9"/>
|
||||
<symbol name="Y13R" address="RAM:02DA"/>
|
||||
<symbol name="Y13R" address="RAM:02DB"/>
|
||||
<symbol name="Y14R" address="RAM:02DC"/>
|
||||
<symbol name="Y14R" address="RAM:02DD"/>
|
||||
<symbol name="Y15R" address="RAM:02DE"/>
|
||||
<symbol name="Y15R" address="RAM:02DF"/>
|
||||
<symbol name="XYC" address="RAM:02E0"/>
|
||||
<symbol name="U4SMR3" address="RAM:02F5"/>
|
||||
<symbol name="U4SMR2" address="RAM:02F6"/>
|
||||
<symbol name="U4SMR" address="RAM:02F7"/>
|
||||
<symbol name="U4MR" address="RAM:02F8"/>
|
||||
<symbol name="U4BRG" address="RAM:02F9"/>
|
||||
<symbol name="U4TB" address="RAM:02FA"/>
|
||||
<symbol name="U4TB" address="RAM:02FB"/>
|
||||
<symbol name="U4C0" address="RAM:02FC"/>
|
||||
<symbol name="U4C1" address="RAM:02FD"/>
|
||||
<symbol name="U4RB" address="RAM:02FE"/>
|
||||
<symbol name="U4RB" address="RAM:02FF"/>
|
||||
<symbol name="TBSR" address="RAM:0300"/>
|
||||
<symbol name="TA11" address="RAM:0302"/>
|
||||
<symbol name="TA11" address="RAM:0303"/>
|
||||
<symbol name="TA21" address="RAM:0304"/>
|
||||
<symbol name="TA21" address="RAM:0305"/>
|
||||
<symbol name="TA41" address="RAM:0306"/>
|
||||
<symbol name="TA41" address="RAM:0307"/>
|
||||
<symbol name="INVC0" address="RAM:0308"/>
|
||||
<symbol name="INVC1" address="RAM:0309"/>
|
||||
<symbol name="IDB0" address="RAM:030A"/>
|
||||
<symbol name="IDB1" address="RAM:030B"/>
|
||||
<symbol name="DTT" address="RAM:030C"/>
|
||||
<symbol name="ICTB2" address="RAM:030D"/>
|
||||
<symbol name="TB3" address="RAM:0310"/>
|
||||
<symbol name="TB3" address="RAM:0311"/>
|
||||
<symbol name="TB4" address="RAM:0312"/>
|
||||
<symbol name="TB4" address="RAM:0313"/>
|
||||
<symbol name="TB5" address="RAM:0314"/>
|
||||
<symbol name="TB5" address="RAM:0315"/>
|
||||
<symbol name="TB3MR" address="RAM:031B"/>
|
||||
<symbol name="TB4MR" address="RAM:031C"/>
|
||||
<symbol name="TB5MR" address="RAM:031D"/>
|
||||
<symbol name="IFSR" address="RAM:031F"/>
|
||||
<symbol name="U3SMR3" address="RAM:0325"/>
|
||||
<symbol name="U3SMR2" address="RAM:0326"/>
|
||||
<symbol name="U3SMR" address="RAM:0327"/>
|
||||
<symbol name="U3MR" address="RAM:0328"/>
|
||||
<symbol name="U3BRG" address="RAM:0329"/>
|
||||
<symbol name="U3TB" address="RAM:032A"/>
|
||||
<symbol name="U3TB" address="RAM:032B"/>
|
||||
<symbol name="U3C0" address="RAM:032C"/>
|
||||
<symbol name="U3C1" address="RAM:032D"/>
|
||||
<symbol name="U3RB" address="RAM:032E"/>
|
||||
<symbol name="U3RB" address="RAM:032F"/>
|
||||
<symbol name="U2SMR3" address="RAM:0335"/>
|
||||
<symbol name="U2SMR2" address="RAM:0336"/>
|
||||
<symbol name="U2SMR" address="RAM:0337"/>
|
||||
<symbol name="U2MR" address="RAM:0338"/>
|
||||
<symbol name="U2BRG" address="RAM:0339"/>
|
||||
<symbol name="U2TB" address="RAM:033A"/>
|
||||
<symbol name="U2TB" address="RAM:033B"/>
|
||||
<symbol name="U2C0" address="RAM:033C"/>
|
||||
<symbol name="U2C1" address="RAM:033D"/>
|
||||
<symbol name="U2RB" address="RAM:033E"/>
|
||||
<symbol name="U2RB" address="RAM:033F"/>
|
||||
<symbol name="TABSR" address="RAM:0340"/>
|
||||
<symbol name="CPSRF" address="RAM:0341"/>
|
||||
<symbol name="ONSF" address="RAM:0342"/>
|
||||
<symbol name="TGSR" address="RAM:0343"/>
|
||||
<symbol name="UDF" address="RAM:0344"/>
|
||||
<symbol name="TA0" address="RAM:0346"/>
|
||||
<symbol name="TA0" address="RAM:0347"/>
|
||||
<symbol name="TA1" address="RAM:0348"/>
|
||||
<symbol name="TA1" address="RAM:0349"/>
|
||||
<symbol name="TA2" address="RAM:034A"/>
|
||||
<symbol name="TA2" address="RAM:034B"/>
|
||||
<symbol name="TA3" address="RAM:034C"/>
|
||||
<symbol name="TA3" address="RAM:034D"/>
|
||||
<symbol name="TA4" address="RAM:034E"/>
|
||||
<symbol name="TA4" address="RAM:034F"/>
|
||||
<symbol name="TB0" address="RAM:0350"/>
|
||||
<symbol name="TB0" address="RAM:0351"/>
|
||||
<symbol name="TB1" address="RAM:0352"/>
|
||||
<symbol name="TB1" address="RAM:0353"/>
|
||||
<symbol name="TB2" address="RAM:0354"/>
|
||||
<symbol name="TB2" address="RAM:0355"/>
|
||||
<symbol name="TA0MR" address="RAM:0356"/>
|
||||
<symbol name="TA1MR" address="RAM:0357"/>
|
||||
<symbol name="TA2MR" address="RAM:0358"/>
|
||||
<symbol name="TA3MR" address="RAM:0359"/>
|
||||
<symbol name="TA4MR" address="RAM:035A"/>
|
||||
<symbol name="TB0MR" address="RAM:035B"/>
|
||||
<symbol name="TB1MR" address="RAM:035C"/>
|
||||
<symbol name="TB2MR" address="RAM:035D"/>
|
||||
<symbol name="U0MR" address="RAM:0360"/>
|
||||
<symbol name="U0BRG" address="RAM:0361"/>
|
||||
<symbol name="U0TB" address="RAM:0362"/>
|
||||
<symbol name="U0TB" address="RAM:0363"/>
|
||||
<symbol name="U0C0" address="RAM:0364"/>
|
||||
<symbol name="U0C1" address="RAM:0365"/>
|
||||
<symbol name="U0RB" address="RAM:0366"/>
|
||||
<symbol name="U0RB" address="RAM:0367"/>
|
||||
<symbol name="U1MR" address="RAM:0367"/>
|
||||
<symbol name="U1BRG" address="RAM:0369"/>
|
||||
<symbol name="U1TB" address="RAM:036A"/>
|
||||
<symbol name="U1TB" address="RAM:036B"/>
|
||||
<symbol name="U1C0" address="RAM:036C"/>
|
||||
<symbol name="U1C1" address="RAM:036D"/>
|
||||
<symbol name="U1RB" address="RAM:036E"/>
|
||||
<symbol name="U1RB" address="RAM:036F"/>
|
||||
<symbol name="FMR1" address="RAM:0376"/>
|
||||
<symbol name="FMR0" address="RAM:0377"/>
|
||||
<symbol name="DM0SL" address="RAM:0378"/>
|
||||
<symbol name="DM1SL" address="RAM:0379"/>
|
||||
<symbol name="DM2SL" address="RAM:037A"/>
|
||||
<symbol name="DM3SL" address="RAM:037B"/>
|
||||
<symbol name="CRCD" address="RAM:037C"/>
|
||||
<symbol name="CRCD" address="RAM:037D"/>
|
||||
<symbol name="CRCIN" address="RAM:037E"/>
|
||||
<symbol name="AD0" address="RAM:0380"/>
|
||||
<symbol name="AD0" address="RAM:0381"/>
|
||||
<symbol name="AD1" address="RAM:0382"/>
|
||||
<symbol name="AD1" address="RAM:0383"/>
|
||||
<symbol name="AD2" address="RAM:0384"/>
|
||||
<symbol name="AD2" address="RAM:0385"/>
|
||||
<symbol name="AD3" address="RAM:0386"/>
|
||||
<symbol name="AD3" address="RAM:0387"/>
|
||||
<symbol name="AD4" address="RAM:0388"/>
|
||||
<symbol name="AD4" address="RAM:0389"/>
|
||||
<symbol name="AD5" address="RAM:038A"/>
|
||||
<symbol name="AD5" address="RAM:039B"/>
|
||||
<symbol name="AD6" address="RAM:039C"/>
|
||||
<symbol name="AD6" address="RAM:039D"/>
|
||||
<symbol name="AD7" address="RAM:039E"/>
|
||||
<symbol name="AD7" address="RAM:039F"/>
|
||||
<symbol name="ADCON2" address="RAM:0394"/>
|
||||
<symbol name="ADCON0" address="RAM:0396"/>
|
||||
<symbol name="ADCON1" address="RAM:0397"/>
|
||||
<symbol name="DA0" address="RAM:0398"/>
|
||||
<symbol name="DA1" address="RAM:039A"/>
|
||||
<symbol name="DACON" address="RAM:039C"/>
|
||||
<symbol name="PSC" address="RAM:03AF"/>
|
||||
<symbol name="PS0" address="RAM:03B0"/>
|
||||
<symbol name="PS1" address="RAM:03B1"/>
|
||||
<symbol name="PSL0" address="RAM:03B2"/>
|
||||
<symbol name="PSL1" address="RAM:03B3"/>
|
||||
<symbol name="PS2" address="RAM:03B4"/>
|
||||
<symbol name="PS3" address="RAM:03B5"/>
|
||||
<symbol name="PSL2" address="RAM:03B6"/>
|
||||
<symbol name="PSL3" address="RAM:03B7"/>
|
||||
<symbol name="P6" address="RAM:03C0"/>
|
||||
<symbol name="P7" address="RAM:03C1"/>
|
||||
<symbol name="PD6" address="RAM:03C2"/>
|
||||
<symbol name="PD7" address="RAM:03C3"/>
|
||||
<symbol name="P8" address="RAM:03C4"/>
|
||||
<symbol name="P9" address="RAM:03C5"/>
|
||||
<symbol name="PD8" address="RAM:03C6"/>
|
||||
<symbol name="PD9" address="RAM:03C7"/>
|
||||
<symbol name="P10" address="RAM:03C8"/>
|
||||
<symbol name="PD10" address="RAM:03CA"/>
|
||||
<symbol name="PUR2" address="RAM:03DA"/>
|
||||
<symbol name="PUR3" address="RAM:03DB"/>
|
||||
<symbol name="P0" address="RAM:03E0"/>
|
||||
<symbol name="P1" address="RAM:03E1"/>
|
||||
<symbol name="PD0" address="RAM:03E2"/>
|
||||
<symbol name="PD1" address="RAM:03E3"/>
|
||||
<symbol name="P2" address="RAM:03E4"/>
|
||||
<symbol name="P3" address="RAM:03E5"/>
|
||||
<symbol name="PD2" address="RAM:03E6"/>
|
||||
<symbol name="PD3" address="RAM:03E7"/>
|
||||
<symbol name="P4" address="RAM:03E8"/>
|
||||
<symbol name="P5" address="RAM:03E9"/>
|
||||
<symbol name="PD4" address="RAM:03EA"/>
|
||||
<symbol name="PD5" address="RAM:03EB"/>
|
||||
<symbol name="PUR0" address="RAM:03F0"/>
|
||||
<symbol name="PUR1" address="RAM:03F1"/>
|
||||
<symbol name="PCR" address="RAM:03FF"/>
|
||||
<symbol name="UNDEFINED_INSTRUCTION_INT_VECTOR" address="RAM:FFFFDC" entry="true" type="code_ptr"/>
|
||||
<symbol name="OVERFLOW_INTO_VECTOR" address="RAM:FFFFE0" entry="true" type="code_ptr"/>
|
||||
<symbol name="BRK_INSTRUCTION_INT_VECTOR" address="RAM:FFFFE4" entry="true" type="code_ptr"/>
|
||||
<symbol name="ADDRESS_MATCH_INT_VECTOR" address="RAM:FFFFE8" entry="true" type="code_ptr"/>
|
||||
<symbol name="SINGLE_STEP_INT_VECTOR" address="RAM:FFFFEC" entry="true" type="code_ptr"/>
|
||||
<symbol name="WATCHDOG_TIMER_INT_VECTOR" address="RAM:FFFFF0" entry="true" type="code_ptr"/>
|
||||
<symbol name="NOT_DBC_INT_VECTOR" address="RAM:FFFFF4" entry="true" type="code_ptr"/>
|
||||
<symbol name="NOT_NMI_INT_VECTOR" address="RAM:FFFFF8" entry="true" type="code_ptr"/>
|
||||
<symbol name="RESET_INT_VECTOR" address="RAM:FFFFFC" eentry="true" type="code_ptr"/>
|
||||
</default_symbols>
|
||||
<default_memory_blocks>
|
||||
<memory_block name="SFR" start_address="RAM:0000" mode="rw" length="0x03FF" initialized="false"/>
|
||||
</default_memory_blocks>
|
||||
</processor_spec>
|
||||
5050
Ghidra/Processors/M16C/data/languages/M16C_80.slaspec
Normal file
5050
Ghidra/Processors/M16C/data/languages/M16C_80.slaspec
Normal file
File diff suppressed because it is too large
Load Diff
95
Ghidra/Processors/M16C/data/manuals/M16C_60.idx
Normal file
95
Ghidra/Processors/M16C/data/manuals/M16C_60.idx
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
@m16csm.pdf
|
||||
ABS, 55
|
||||
ADC, 56
|
||||
ADCF, 57
|
||||
ADD, 58
|
||||
ADJNZ, 60
|
||||
AND, 61
|
||||
BAND, 63
|
||||
BCLR, 64
|
||||
BM, 65
|
||||
BNAND, 66
|
||||
BNOR, 67
|
||||
BNOT, 68
|
||||
BNTST, 69
|
||||
BNXOR, 70
|
||||
BOR, 71
|
||||
BRK, 72
|
||||
BSET, 73
|
||||
BTST, 74
|
||||
BTSTC, 75
|
||||
BTSTS, 76
|
||||
BXOR, 77
|
||||
CMP, 78
|
||||
DADC, 80
|
||||
DADD, 81
|
||||
DEC, 82
|
||||
DIV, 83
|
||||
DIVU, 84
|
||||
DIVX, 85
|
||||
DSBB, 86
|
||||
DSUB, 87
|
||||
ENTER, 88
|
||||
EXITD, 89
|
||||
EXTS, 90
|
||||
FCLR, 91
|
||||
FSET, 92
|
||||
INC, 93
|
||||
INT, 94
|
||||
INTO, 95
|
||||
J, 96
|
||||
JMP, 97
|
||||
JMPI, 98
|
||||
JMPS, 99
|
||||
JSR, 100
|
||||
JSRI, 101
|
||||
JSRS, 102
|
||||
LDC, 103
|
||||
LDCTX, 104
|
||||
LDE, 105
|
||||
LDINTB, 106
|
||||
LDIPL, 107
|
||||
MOV, 108
|
||||
MOVA, 110
|
||||
MOVHH, 111
|
||||
MOVHL, 111
|
||||
MOVLH, 111
|
||||
MOVLL, 111
|
||||
MUL, 112
|
||||
MULU, 113
|
||||
NEG, 114
|
||||
NOP, 115
|
||||
NOT, 116
|
||||
OR, 117
|
||||
POP, 119
|
||||
POPC, 120
|
||||
POPM, 121
|
||||
PUSH, 122
|
||||
PUSHA, 123
|
||||
PUSHC, 124
|
||||
PUSHM, 125
|
||||
REIT, 126
|
||||
RMPA, 127
|
||||
ROLC, 128
|
||||
RORC, 129
|
||||
ROT, 130
|
||||
RTS, 131
|
||||
SBB, 132
|
||||
SBJNZ, 133
|
||||
SHA, 134
|
||||
SHL, 135
|
||||
SMOVB, 136
|
||||
SMOVF, 137
|
||||
SSTR, 138
|
||||
STC, 139
|
||||
STCTX, 140
|
||||
STE, 141
|
||||
STNZ, 142
|
||||
STZ, 143
|
||||
STZX, 144
|
||||
SUB, 145
|
||||
TST, 147
|
||||
UND, 148
|
||||
WAIT, 149
|
||||
XCHG, 150
|
||||
XOR, 151
|
||||
110
Ghidra/Processors/M16C/data/manuals/M16C_80.idx
Normal file
110
Ghidra/Processors/M16C/data/manuals/M16C_80.idx
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
@m16c80.pdf
|
||||
ABS, 60
|
||||
ADC, 61
|
||||
ADCF, 62
|
||||
ADD, 63
|
||||
ADDX, 65
|
||||
ADJNZ, 66
|
||||
AND, 67
|
||||
BAND, 69
|
||||
BCLR, 70
|
||||
BITINDEX, 71
|
||||
BM, 72
|
||||
BNAND, 73
|
||||
BNOR, 74
|
||||
BNOT, 75
|
||||
BNTST, 76
|
||||
BNXOR, 77
|
||||
BOR, 78
|
||||
BRK, 79
|
||||
BRK2, 80
|
||||
BSET, 81
|
||||
BTST, 82
|
||||
BTSTC, 83
|
||||
BTSTS, 84
|
||||
BXOR, 85
|
||||
CLIP, 86
|
||||
CMP, 87
|
||||
CMPX, 89
|
||||
DADC, 90
|
||||
DADD, 91
|
||||
DEC, 92
|
||||
DIV, 93
|
||||
DIVU, 94
|
||||
DIVX, 95
|
||||
DSBB, 96
|
||||
DSUB, 97
|
||||
ENTER, 98
|
||||
EXITD, 99
|
||||
EXTS, 100
|
||||
EXTZ, 101
|
||||
FLCR, 102
|
||||
FREIT, 103
|
||||
FSET, 104
|
||||
INC, 105
|
||||
INDEX, 175
|
||||
INT, 107
|
||||
INTO, 108
|
||||
J, 109
|
||||
JMP, 110
|
||||
JMPI, 111
|
||||
JMPS, 112
|
||||
JSR, 113
|
||||
JSRI, 114
|
||||
JSRS, 115
|
||||
LDC, 116
|
||||
LDCTX, 117
|
||||
LDIPL, 118
|
||||
MAX, 119
|
||||
MIN, 120
|
||||
MOV, 121
|
||||
MOVA, 123
|
||||
MOVHH, 124
|
||||
MOVHL, 124
|
||||
MOVLH, 124
|
||||
MOVLL, 124
|
||||
MOVX, 125
|
||||
MUL, 126
|
||||
MULEX, 127
|
||||
MULU, 128
|
||||
NEG, 129
|
||||
NOP, 130
|
||||
NOT, 131
|
||||
OR, 132
|
||||
POP, 134
|
||||
POPC, 135
|
||||
POPM, 136
|
||||
PUSH, 137
|
||||
PUSHA, 138
|
||||
PUSHC, 139
|
||||
PUSHM, 140
|
||||
REIT, 141
|
||||
RMPA, 142
|
||||
ROLC, 143
|
||||
RORC, 144
|
||||
ROT, 145
|
||||
RTS, 146
|
||||
SBB, 147
|
||||
SBJNZ, 148
|
||||
SC, 149
|
||||
SCMPU, 150
|
||||
SHA, 151
|
||||
SHL, 153
|
||||
SIN, 155
|
||||
SMOVB, 156
|
||||
SMOVF, 157
|
||||
SMOVU, 158
|
||||
SOUT, 159
|
||||
SSTR, 160
|
||||
STC, 161
|
||||
STCTX, 162
|
||||
STNZ, 163
|
||||
STZ, 164
|
||||
STZX, 165
|
||||
SUB, 166
|
||||
SUBX, 168
|
||||
TST, 169
|
||||
UND, 171
|
||||
WAIT, 172
|
||||
XCHG, 173
|
||||
XOR, 174
|
||||
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