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Feature: Add support for HC11 microcontrollers
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Ghidra/Processors/HC11/Module.manifest
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Ghidra/Processors/HC11/Module.manifest
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Ghidra/Processors/HC11/build.gradle
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Ghidra/Processors/HC11/build.gradle
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/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
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apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
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apply plugin: 'eclipse'
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eclipse.project.name = 'Processors HC11'
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sleighCompileOptions = [
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'-l'
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]
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Ghidra/Processors/HC11/certification.manifest
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Ghidra/Processors/HC11/certification.manifest
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##VERSION: 2.0
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Module.manifest||GHIDRA||||END|
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data/languages/HC11.cspec||GHIDRA||||END|
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data/languages/HC11.ldefs||GHIDRA||||END|
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data/languages/HC11.opinion||GHIDRA||||END|
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data/languages/HC11.pspec||GHIDRA||||END|
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data/languages/HC11.slaspec||GHIDRA||||END|
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Ghidra/Processors/HC11/data/languages/HC11.cspec
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Ghidra/Processors/HC11/data/languages/HC11.cspec
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<data_organization> <!-- These tags need to be verified -->
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<absolute_max_alignment value="0" />
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<machine_alignment value="1" />
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<default_alignment value="1" />
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<pointer_size value="2" />
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<wchar_size value="4" />
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<short_size value="2" />
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<integer_size value="4" />
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<long_size value="4" />
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<long_long_size value="8" />
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<float_size value="4" />
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<double_size value="8" />
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<long_double_size value="8" />
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</data_organization>
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<global>
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<range space="RAM"/>
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</global>
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<stackpointer register="SP" space="RAM" growth="negative"/>
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<default_proto>
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<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
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<input>
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<pentry minsize="1" maxsize="1">
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<register name="A"/>
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</pentry>
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<pentry minsize="1" maxsize="1">
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<register name="B"/>
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</pentry>
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<pentry minsize="2" maxsize="2">
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<register name="D"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IY"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IX"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="2" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="2">
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<register name="D"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>
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</unaffected>
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</prototype>
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</default_proto>
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</compiler_spec>
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Ghidra/Processors/HC11/data/languages/HC11.ldefs
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Ghidra/Processors/HC11/data/languages/HC11.ldefs
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<?xml version="1.0" encoding="UTF-8"?>
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<language_definitions>
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<language processor="HC-11"
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endian="big"
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size="16"
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variant="default"
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version="2.0"
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slafile="HC11.sla"
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processorspec="HC11.pspec"
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id="HC-11:BE:16:default">
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<description>HC11 Microcontroller Family</description>
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<compiler name="default" spec="HC11.cspec" id="default"/>
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<external_name tool="gnu" name="m68hc11"/>
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</language>
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</language_definitions>
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Ghidra/Processors/HC11/data/languages/HC11.opinion
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Ghidra/Processors/HC11/data/languages/HC11.opinion
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<opinions>
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<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
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<constraint primary="70" processor="HC11" endian="big" size="16" variant="default"/>
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</constraint>
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</opinions>
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Ghidra/Processors/HC11/data/languages/HC11.pspec
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Ghidra/Processors/HC11/data/languages/HC11.pspec
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<?xml version="1.0" encoding="UTF-8"?>
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<processor_spec>
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<programcounter register="PC"/>
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<default_symbols>
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<symbol name="VECTOR_Reset" address="FFFE" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_ClockMonitorFailReset" address="FFFC" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_COPFailureReset" address="FFFA" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_UnimplementedInstructionTrap" address="FFF8" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_SWI" address="FFF6" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_XIRQ" address="FFF4" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_IRQ" address="FFF2" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_RealTimeInterrupt" address="FFF0" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerInputCapture1" address="FFEE" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerInputCapture2" address="FFEC" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerInputCapture3" address="FFEA" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOutputCompare1" address="FFE8" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOutputCompare2" address="FFE6" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOutputCompare3" address="FFE4" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOutputCompare4" address="FFE2" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOutputCompare5" address="FFE0" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_TimerOverflow" address="FFDE" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_PulseAccumulatorAOverflow" address="FFDC" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_PulseAccumulatorInputEdge" address="FFDA" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_SPI" address="FFD8" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_SCI" address="FFD6" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFD4" address="FFD4" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFD2" address="FFD2" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFD0" address="FFD0" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFCE" address="FFCE" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFCC" address="FFCC" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFCA" address="FFCA" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFC8" address="FFC8" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFC6" address="FFC6" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFC4" address="FFC4" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFC2" address="FFC2" entry="true" type="code_ptr"/>
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<symbol name="VECTOR_Reserved_FFC0" address="FFC0" entry="true" type="code_ptr"/>
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</default_symbols>
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</processor_spec>
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Ghidra/Processors/HC11/data/languages/HC11.slaspec
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2464
Ghidra/Processors/HC11/data/languages/HC11.slaspec
Normal file
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