diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/subflow.cc b/Ghidra/Features/Decompiler/src/decompile/cpp/subflow.cc index bde73ee843..b6917f31fd 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/subflow.cc +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/subflow.cc @@ -1515,6 +1515,8 @@ bool SplitFlow::addOp(PcodeOp *op,TransformVar *rvn,int4 slot) if (op->code() == CPUI_INDIRECT) { opSetInput(loOp,newIop(op->getIn(1)),1); opSetInput(hiOp,newIop(op->getIn(1)),1); + loOp->inheritIndirect(op); + hiOp->inheritIndirect(op); numParam = 1; } for(int4 i=0;iisIndirectCreation()) { + if (indOp->getIn(0)->isIndirectZero()) + special |= TransformOp::indirect_creation; + else + special |= TransformOp::indirect_creation_possible_out; + } +} + void LanedRegister::LanedIterator::normalize(void) { diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/transform.hh b/Ghidra/Features/Decompiler/src/decompile/cpp/transform.hh index e8cf9877a0..08462ed07c 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/transform.hh +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/transform.hh @@ -87,6 +87,7 @@ private: public: TransformVar *getOut(void) const { return output; } ///< Get the output placeholder variable for \b this operator TransformVar *getIn(int4 i) const { return input[i]; } ///< Get the i-th input placeholder variable for \b this + void inheritIndirect(PcodeOp *indOp); ///< Set \e indirect \e creation flags for \b this based on given INDIRECT }; /// \brief Describes a (register) storage location and the ways it might be split into lanes