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AA64: Change eor3 OR to XOR

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Sleigh-InSPECtor 2024-04-18 23:37:25 +09:30
parent cae9190c13
commit a3d13679e9
1 changed files with 32 additions and 32 deletions
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64
Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
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@ -2710,39 +2710,39 @@ is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B
is b_2131=0b11001110000 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rm_VPR128.16B | Ra_VPR128.16B on lane size 1
TMPQ1[0,8] = Rm_VPR128.16B[0,8] | Ra_VPR128.16B[0,8];
TMPQ1[8,8] = Rm_VPR128.16B[8,8] | Ra_VPR128.16B[8,8];
TMPQ1[16,8] = Rm_VPR128.16B[16,8] | Ra_VPR128.16B[16,8];
TMPQ1[24,8] = Rm_VPR128.16B[24,8] | Ra_VPR128.16B[24,8];
TMPQ1[32,8] = Rm_VPR128.16B[32,8] | Ra_VPR128.16B[32,8];
TMPQ1[40,8] = Rm_VPR128.16B[40,8] | Ra_VPR128.16B[40,8];
TMPQ1[48,8] = Rm_VPR128.16B[48,8] | Ra_VPR128.16B[48,8];
TMPQ1[56,8] = Rm_VPR128.16B[56,8] | Ra_VPR128.16B[56,8];
TMPQ1[64,8] = Rm_VPR128.16B[64,8] | Ra_VPR128.16B[64,8];
TMPQ1[72,8] = Rm_VPR128.16B[72,8] | Ra_VPR128.16B[72,8];
TMPQ1[80,8] = Rm_VPR128.16B[80,8] | Ra_VPR128.16B[80,8];
TMPQ1[88,8] = Rm_VPR128.16B[88,8] | Ra_VPR128.16B[88,8];
TMPQ1[96,8] = Rm_VPR128.16B[96,8] | Ra_VPR128.16B[96,8];
TMPQ1[104,8] = Rm_VPR128.16B[104,8] | Ra_VPR128.16B[104,8];
TMPQ1[112,8] = Rm_VPR128.16B[112,8] | Ra_VPR128.16B[112,8];
TMPQ1[120,8] = Rm_VPR128.16B[120,8] | Ra_VPR128.16B[120,8];
TMPQ1[0,8] = Rm_VPR128.16B[0,8] ^ Ra_VPR128.16B[0,8];
TMPQ1[8,8] = Rm_VPR128.16B[8,8] ^ Ra_VPR128.16B[8,8];
TMPQ1[16,8] = Rm_VPR128.16B[16,8] ^ Ra_VPR128.16B[16,8];
TMPQ1[24,8] = Rm_VPR128.16B[24,8] ^ Ra_VPR128.16B[24,8];
TMPQ1[32,8] = Rm_VPR128.16B[32,8] ^ Ra_VPR128.16B[32,8];
TMPQ1[40,8] = Rm_VPR128.16B[40,8] ^ Ra_VPR128.16B[40,8];
TMPQ1[48,8] = Rm_VPR128.16B[48,8] ^ Ra_VPR128.16B[48,8];
TMPQ1[56,8] = Rm_VPR128.16B[56,8] ^ Ra_VPR128.16B[56,8];
TMPQ1[64,8] = Rm_VPR128.16B[64,8] ^ Ra_VPR128.16B[64,8];
TMPQ1[72,8] = Rm_VPR128.16B[72,8] ^ Ra_VPR128.16B[72,8];
TMPQ1[80,8] = Rm_VPR128.16B[80,8] ^ Ra_VPR128.16B[80,8];
TMPQ1[88,8] = Rm_VPR128.16B[88,8] ^ Ra_VPR128.16B[88,8];
TMPQ1[96,8] = Rm_VPR128.16B[96,8] ^ Ra_VPR128.16B[96,8];
TMPQ1[104,8] = Rm_VPR128.16B[104,8] ^ Ra_VPR128.16B[104,8];
TMPQ1[112,8] = Rm_VPR128.16B[112,8] ^ Ra_VPR128.16B[112,8];
TMPQ1[120,8] = Rm_VPR128.16B[120,8] ^ Ra_VPR128.16B[120,8];
# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] ^ TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] ^ TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] ^ TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] ^ TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] ^ TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] ^ TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] ^ TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] ^ TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] ^ TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] ^ TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] ^ TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] ^ TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] ^ TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] ^ TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] ^ TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] ^ TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}