mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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Add support for ARCompact instruction set
ARCompact is the instruction set which was used in some versions of
Intel's Management Engine, in some versions of Lenovo's Thinkpad
Embedded Controller and some versions of Intel's Wireless-AC chips.
This commit squashed commits from the initial submission on
https://github.com/NationalSecurityAgency/ghidra/pull/3006.
The full history is still available on
27fbe7278d...arcompact_on_9.1.2
This commit is contained in:
Nicolas Iooss
parent
ec34e0ed6e
commit
94bae1a917
@ -718,3 +718,11 @@ PCodeTest({
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'language_id': 'Xtensa:BE:32:default',
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'ccflags': '-L %(toolchain_dir)s/lib/gcc/xtensa-elf/%(gcc_version)s',
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})
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PCodeTest({
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'name': 'ARC700',
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'build_all': 1,
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'toolchain': 'ARC/arc700-elf',
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'language_id': 'ARCompact:LE:32:default',
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'ccflags': '-mcpu=arc700 -lgcc',
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})
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0
Ghidra/Processors/ARC/Module.manifest
Normal file
0
Ghidra/Processors/ARC/Module.manifest
Normal file
26
Ghidra/Processors/ARC/build.gradle
Normal file
26
Ghidra/Processors/ARC/build.gradle
Normal file
@ -0,0 +1,26 @@
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/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
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apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
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apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
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apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
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apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
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apply plugin: 'eclipse'
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eclipse.project.name = 'Processors ARC'
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dependencies {
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api project(':Base')
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}
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157
Ghidra/Processors/ARC/data/languages/ARCompact.cspec
Normal file
157
Ghidra/Processors/ARC/data/languages/ARCompact.cspec
Normal file
@ -0,0 +1,157 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<compiler_spec>
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<data_organization> <!-- These tags were copied from https://github.com/xyzz/ghidra-mep -->
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<absolute_max_alignment value="0" />
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<machine_alignment value="2" />
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<default_alignment value="1" />
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<default_pointer_alignment value="4" />
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<pointer_size value="4" />
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<wchar_size value="4" />
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<short_size value="2" />
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<integer_size value="4" />
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<long_size value="4" />
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<long_long_size value="8" />
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<float_size value="4" />
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<double_size value="8" />
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<long_double_size value="8" />
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<size_alignment_map>
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<entry size="1" alignment="1" />
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<entry size="2" alignment="2" />
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<entry size="4" alignment="4" />
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<entry size="8" alignment="8" />
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</size_alignment_map>
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</data_organization>
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<global>
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<range space="ram"/>
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<range space="auxregs"/>
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</global>
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<stackpointer register="sp" space="ram"/>
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<funcptr align="2"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="0" stackshift="0">
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<input>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r0"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r1"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r2"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r3"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r5"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r7"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r0"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r1" piece2="r0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="r13"/>
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<register name="r14"/>
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<register name="r15"/>
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<register name="r16"/>
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<register name="r17"/>
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<register name="r18"/>
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<register name="r19"/>
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<register name="r20"/>
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<register name="r21"/>
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<register name="r22"/>
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<register name="r23"/>
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<register name="r25"/>
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<register name="gp"/>
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<register name="fp"/>
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<register name="sp"/>
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</unaffected>
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</prototype>
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</default_proto>
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<prototype name="__stdcall64" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r0"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r1"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r1" piece2="r0"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r2"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r3"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r3" piece2="r2"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r5"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r5" piece2="r4"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r7"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r7" piece2="r6"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="4">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4" extension="inttype">
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<register name="r0"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="r1" piece2="r0"/>
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</pentry>
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</output>
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<unaffected>
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<register name="r13"/>
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<register name="r14"/>
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<register name="r15"/>
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<register name="r16"/>
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<register name="r17"/>
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<register name="r18"/>
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<register name="r19"/>
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<register name="r20"/>
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<register name="r21"/>
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<register name="r22"/>
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<register name="r23"/>
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<register name="r25"/>
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<register name="gp"/>
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<register name="fp"/>
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<register name="sp"/>
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</unaffected>
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</prototype>
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</compiler_spec>
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19
Ghidra/Processors/ARC/data/languages/ARCompact.dwarf
Normal file
19
Ghidra/Processors/ARC/data/languages/ARCompact.dwarf
Normal file
@ -0,0 +1,19 @@
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<dwarf>
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<register_mappings>
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<register_mapping dwarf="0" ghidra="r0" auto_count="26"/> <!-- r0..r25 -->
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<register_mapping dwarf="26" ghidra="gp"/>
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<register_mapping dwarf="27" ghidra="fp"/>
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<register_mapping dwarf="28" ghidra="sp" stackpointer="true"/>
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<register_mapping dwarf="29" ghidra="ilink1"/>
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<register_mapping dwarf="30" ghidra="blink"/>
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<register_mapping dwarf="31" ghidra="ilink2"/>
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<register_mapping dwarf="32" ghidra="r32" auto_count="25"/> <!-- r32..r56 -->
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<register_mapping dwarf="57" ghidra="mlo"/>
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<register_mapping dwarf="58" ghidra="mmid"/>
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<register_mapping dwarf="59" ghidra="mhi"/>
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<register_mapping dwarf="60" ghidra="lp_count"/>
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<!-- r61 is reserved and r62 is the long immediate data indicator -->
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<register_mapping dwarf="63" ghidra="pcl"/>
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</register_mappings>
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<call_frame_cfa value="0"/>
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</dwarf>
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17
Ghidra/Processors/ARC/data/languages/ARCompact.ldefs
Normal file
17
Ghidra/Processors/ARC/data/languages/ARCompact.ldefs
Normal file
@ -0,0 +1,17 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->
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<language_definitions>
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<language processor="ARCompact"
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endian="little"
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size="32"
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variant="default"
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version="1.0"
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slafile="ARCompact.sla"
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processorspec="ARCompact.pspec"
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id="ARCompact:LE:32:default">
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<description>ARCompact microcontroller</description>
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<compiler name="default" spec="ARCompact.cspec" id="default"/>
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<external_name tool="DWARF.register.mapping.file" name="ARCompact.dwarf"/>
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</language>
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</language_definitions>
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5
Ghidra/Processors/ARC/data/languages/ARCompact.opinion
Normal file
5
Ghidra/Processors/ARC/data/languages/ARCompact.opinion
Normal file
@ -0,0 +1,5 @@
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<opinions>
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<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
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<constraint primary="93" processor="ARCompact" size="32" />
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</constraint>
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</opinions>
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290
Ghidra/Processors/ARC/data/languages/ARCompact.pspec
Normal file
290
Ghidra/Processors/ARC/data/languages/ARCompact.pspec
Normal file
@ -0,0 +1,290 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->
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<processor_spec>
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<properties>
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<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARCompactEmulateInstructionStateModifier"/>
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</properties>
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<programcounter register="pcl"/>
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<volatile outputop="write_volatile" inputop="read_volatile">
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<range space="auxregs" first="0x0" last="0x7"/>
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<!-- do not mark LP_START and LP_END as volatile -->
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<range space="auxregs" first="0x10" last="0xFFFF"/>
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</volatile>
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<default_symbols>
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<symbol name="STATUS" address="auxregs:0000"/>
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<symbol name="SEMAPHORE" address="auxregs:0004"/>
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<symbol name="LP_START" address="auxregs:0008"/>
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<symbol name="LP_END" address="auxregs:000C"/>
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<symbol name="IDENTITY" address="auxregs:0010"/>
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<symbol name="DEBUG" address="auxregs:0014"/>
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<symbol name="PC" address="auxregs:0018"/>
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<symbol name="ADCR" address="auxregs:001C"/>
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<symbol name="APCR" address="auxregs:0020"/>
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<symbol name="ACR" address="auxregs:0024"/>
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<symbol name="STATUS32" address="auxregs:0028"/>
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<symbol name="STATUS32_L1" address="auxregs:002C"/>
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<symbol name="STATUS32_L2" address="auxregs:0030"/>
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<symbol name="IVIC" address="auxregs:0040"/>
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<symbol name="CHE_MODE" address="auxregs:0044"/>
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<symbol name="MULHI" address="auxregs:0048"/>
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<symbol name="LOCKLINE" address="auxregs:004C"/>
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<symbol name="DMC_CODE_RAM" address="auxregs:0050"/>
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<symbol name="TAG_ADDR_MASK" address="auxregs:0054"/>
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<symbol name="TAG_DATA_MASK" address="auxregs:0058"/>
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<symbol name="LINE_LENGTH_MASK" address="auxregs:005C"/>
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<symbol name="DCCM_BASE" address="auxregs:0060"/>
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<symbol name="UNLOCKLINE" address="auxregs:0064"/>
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<symbol name="IC_RAM_ADDRESS" address="auxregs:0068"/>
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<symbol name="IC_TAG" address="auxregs:006C"/>
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<symbol name="IC_WP" address="auxregs:0070"/>
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<symbol name="IC_DATA" address="auxregs:0074"/>
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<symbol name="IC_PTAG" address="auxregs:0078"/>
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<symbol name="IC_PTAG_HI" address="auxregs:007C"/>
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<symbol name="COUNT0" address="auxregs:0084"/>
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<symbol name="CONTROL0" address="auxregs:0088"/>
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<symbol name="LIMIT0" address="auxregs:008C"/>
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<symbol name="PCPORT" address="auxregs:0090"/>
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<symbol name="INT_VECTOR_BASE" address="auxregs:0094"/>
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<symbol name="AUX_VBFDW_MODE" address="auxregs:0098"/>
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<symbol name="AUX_VBFDW_BM0" address="auxregs:009C"/>
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<symbol name="AUX_VBFDW_BM1" address="auxregs:00A0"/>
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<symbol name="AUX_VBFDW_ACCU" address="auxregs:00A4"/>
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<symbol name="AUX_VBFDW_OFST" address="auxregs:00A8"/>
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<symbol name="AUX_VBFDW_INTSTAT" address="auxregs:00AC"/>
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<symbol name="AUX_XMAC0_24" address="auxregs:00B0"/>
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<symbol name="AUX_XMAC1_24" address="auxregs:00B4"/>
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<symbol name="AUX_XMAC2_24" address="auxregs:00B8"/>
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<symbol name="AUX_FBF_STORE_16" address="auxregs:00BC"/>
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<symbol name="ERP_CTRL" address="auxregs:00FC"/>
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<symbol name="AUX_MACMODE" address="auxregs:0104"/>
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<symbol name="AUX_IRQ_LV12" address="auxregs:010C"/>
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<symbol name="AUX_XMAC0" address="auxregs:0110"/>
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<symbol name="AUX_XMAC1" address="auxregs:0114"/>
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<symbol name="AUX_XMAC2" address="auxregs:0118"/>
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<symbol name="DC_IVDC" address="auxregs:011C"/>
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<symbol name="DC_CTRL" address="auxregs:0120"/>
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<symbol name="DC_LDL" address="auxregs:0124"/>
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<symbol name="DC_IVDL" address="auxregs:0128"/>
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<symbol name="DC_FLSH" address="auxregs:012C"/>
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<symbol name="DC_FLDL" address="auxregs:0130"/>
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<symbol name="DC_STARTR" address="auxregs:0134"/>
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<symbol name="DC_ENDR" address="auxregs:0138"/>
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<symbol name="SWSTAT" address="auxregs:015C"/>
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<symbol name="DC_RAM_ADDR" address="auxregs:0160"/>
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<symbol name="DC_TAG" address="auxregs:0164"/>
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<symbol name="DC_WP" address="auxregs:0168"/>
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<symbol name="DC_DATA" address="auxregs:016C"/>
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<symbol name="DC_PTAG" address="auxregs:0170"/>
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<symbol name="AUX_VOLATILE" address="auxregs:0178"/>
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<symbol name="DC_PTAG_HI" address="auxregs:017C"/>
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<symbol name="BCR_VER" address="auxregs:0180"/>
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<symbol name="DCCM_BASE_BUILD" address="auxregs:0184"/>
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<symbol name="CRC_BUILD" address="auxregs:0188"/>
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<symbol name="BTA_LINK_BUILD" address="auxregs:018C"/>
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<symbol name="VBFDW_BUILD" address="auxregs:0190"/>
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<symbol name="EA_BUILD" address="auxregs:0194"/>
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<symbol name="DATASPACE" address="auxregs:0198"/>
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<symbol name="MEMSUBSYS" address="auxregs:019C"/>
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<symbol name="VECBASE_AC_BUILD" address="auxregs:01A0"/>
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<symbol name="PERIBASE_ADDR" address="auxregs:01A4"/>
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<symbol name="DATA_UNCACHED_BUILD" address="auxregs:01A8"/>
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<symbol name="FP_BUILD" address="auxregs:01AC"/>
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<symbol name="DPFP_BUILD" address="auxregs:01B0"/>
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<symbol name="MPU_BUILD" address="auxregs:01B4"/>
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||||
<symbol name="RF_BUILD" address="auxregs:01B8"/>
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<symbol name="MMU_BUILD" address="auxregs:01BC"/>
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<symbol name="VECBASE_BUILD" address="auxregs:01C4"/>
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<symbol name="D_CACHE_BUILD" address="auxregs:01C8"/>
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<symbol name="MADI_BUILD" address="auxregs:01CC"/>
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<symbol name="DCCM_BUILD" address="auxregs:01D0"/>
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<symbol name="TIMER_BUILD" address="auxregs:01D4"/>
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<symbol name="AP_BUILD" address="auxregs:01D8"/>
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<symbol name="I_CACHE_BUILD" address="auxregs:01DC"/>
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<symbol name="ICCM_BUILD" address="auxregs:01E0"/>
|
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<symbol name="DSPRAM_BUILD" address="auxregs:01E4"/>
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<symbol name="MAC_BUILD" address="auxregs:01E8"/>
|
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<symbol name="MULTIPLY_BUILD" address="auxregs:01EC"/>
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<symbol name="SWAP_BUILD" address="auxregs:01F0"/>
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<symbol name="NORM_BUILD" address="auxregs:01F4"/>
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<symbol name="MINMAX_BUILD" address="auxregs:01F8"/>
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<symbol name="BARREL_BUILD" address="auxregs:01FC"/>
|
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<symbol name="AX0" address="auxregs:0200"/>
|
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<symbol name="AX1" address="auxregs:0204"/>
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<symbol name="AX2" address="auxregs:0208"/>
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<symbol name="AX3" address="auxregs:020C"/>
|
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<symbol name="AY0" address="auxregs:0210"/>
|
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<symbol name="AY1" address="auxregs:0214"/>
|
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<symbol name="AY2" address="auxregs:0218"/>
|
||||
<symbol name="AY3" address="auxregs:021C"/>
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||||
<symbol name="MX00" address="auxregs:0220"/>
|
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<symbol name="MX01" address="auxregs:0224"/>
|
||||
<symbol name="MX10" address="auxregs:0228"/>
|
||||
<symbol name="MX11" address="auxregs:022C"/>
|
||||
<symbol name="MX20" address="auxregs:0230"/>
|
||||
<symbol name="MX21" address="auxregs:0234"/>
|
||||
<symbol name="MX30" address="auxregs:0238"/>
|
||||
<symbol name="MX31" address="auxregs:023C"/>
|
||||
<symbol name="MY00" address="auxregs:0240"/>
|
||||
<symbol name="MY01" address="auxregs:0244"/>
|
||||
<symbol name="MY10" address="auxregs:0248"/>
|
||||
<symbol name="MY11" address="auxregs:024C"/>
|
||||
<symbol name="MY20" address="auxregs:0250"/>
|
||||
<symbol name="MY21" address="auxregs:0254"/>
|
||||
<symbol name="MY30" address="auxregs:0258"/>
|
||||
<symbol name="MY31" address="auxregs:025C"/>
|
||||
<symbol name="XYCONFIG" address="auxregs:0260"/>
|
||||
<symbol name="BURSTSYS" address="auxregs:0264"/>
|
||||
<symbol name="BURSTXYM" address="auxregs:0268"/>
|
||||
<symbol name="BURSTSZ" address="auxregs:026C"/>
|
||||
<symbol name="BURSTVAL" address="auxregs:0270"/>
|
||||
<symbol name="XYLSBASEX" address="auxregs:0274"/>
|
||||
<symbol name="XYLSBASEY" address="auxregs:0278"/>
|
||||
<symbol name="AUX_XMACLW_H" address="auxregs:027C"/>
|
||||
<symbol name="AUX_XMACLW_L" address="auxregs:0280"/>
|
||||
<symbol name="SE_CTRL" address="auxregs:0284"/>
|
||||
<symbol name="SE_STATUS" address="auxregs:0288"/>
|
||||
<symbol name="SE_ERR" address="auxregs:028C"/>
|
||||
<symbol name="SE_EADR" address="auxregs:0290"/>
|
||||
<symbol name="SE_SPC" address="auxregs:0294"/>
|
||||
<symbol name="SDM_BASE" address="auxregs:0298"/>
|
||||
<symbol name="SCM_BASE" address="auxregs:029C"/>
|
||||
<symbol name="SE_DBG_CTRL" address="auxregs:02A0"/>
|
||||
<symbol name="SE_DBG_DATA0" address="auxregs:02A4"/>
|
||||
<symbol name="SE_DBG_DATA1" address="auxregs:02A8"/>
|
||||
<symbol name="SE_DBG_DATA2" address="auxregs:02AC"/>
|
||||
<symbol name="SE_DBG_DATA3" address="auxregs:02B0"/>
|
||||
<symbol name="SE_WATCH" address="auxregs:02B4"/>
|
||||
<symbol name="BPU_BUILD" address="auxregs:0300"/>
|
||||
<symbol name="ISA_CONFIG_BUILD" address="auxregs:0304"/>
|
||||
<symbol name="ERP_BUILD" address="auxregs:031C"/>
|
||||
<symbol name="FP_V2_BUILD" address="auxregs:0320"/>
|
||||
<symbol name="AGU_BUILD" address="auxregs:0330"/>
|
||||
<symbol name="SLC_BUILD" address="auxregs:0338"/>
|
||||
<symbol name="CLUSTER_BUILD" address="auxregs:033C"/>
|
||||
<symbol name="LPB_BUILD" address="auxregs:03A4"/>
|
||||
<symbol name="RTT_BUILD" address="auxregs:03C8"/>
|
||||
<symbol name="IRQ_BUILD" address="auxregs:03CC"/>
|
||||
<symbol name="HWP_BUILD" address="auxregs:03D0"/>
|
||||
<symbol name="PCT_BUILD" address="auxregs:03D4"/>
|
||||
<symbol name="CC_BUILD" address="auxregs:03D8"/>
|
||||
<symbol name="PM_BUILD" address="auxregs:03DC"/>
|
||||
<symbol name="SCQ_SWITCH_BUILD" address="auxregs:03E0"/>
|
||||
<symbol name="VRAPTOR_BUILD" address="auxregs:03E4"/>
|
||||
<symbol name="DMA_CONFIG" address="auxregs:03E8"/>
|
||||
<symbol name="SIMD_CONFIG" address="auxregs:03EC"/>
|
||||
<symbol name="VLC_BUILD" address="auxregs:03F0"/>
|
||||
<symbol name="SIMD_DMA_BUILD" address="auxregs:03F4"/>
|
||||
<symbol name="IFETCH_QUEUE_BUILD" address="auxregs:03F8"/>
|
||||
<symbol name="SMART_BUILD" address="auxregs:03FC"/>
|
||||
<symbol name="COUNT1" address="auxregs:0400"/>
|
||||
<symbol name="CONTROL1" address="auxregs:0404"/>
|
||||
<symbol name="LIMIT1" address="auxregs:0408"/>
|
||||
<symbol name="AUX_IRQ_LEV" address="auxregs:0800"/>
|
||||
<symbol name="AUX_IRQ_HINT" address="auxregs:0804"/>
|
||||
<symbol name="AUX_INTER_CORE_INT" address="auxregs:0808"/>
|
||||
<symbol name="AUX_ICCM" address="auxregs:0820"/>
|
||||
<symbol name="AES_AUX_0" address="auxregs:0840"/>
|
||||
<symbol name="AES_AUX_1" address="auxregs:0844"/>
|
||||
<symbol name="AES_AUX_2" address="auxregs:0848"/>
|
||||
<symbol name="AES_CRYPT_MODE" address="auxregs:084C"/>
|
||||
<symbol name="AES_AUXS" address="auxregs:0850"/>
|
||||
<symbol name="AES_AUXI" address="auxregs:0854"/>
|
||||
<symbol name="AES_AUX_3" address="auxregs:0858"/>
|
||||
<symbol name="AES_AUX_4" address="auxregs:085C"/>
|
||||
<symbol name="ARITH_CTL_AUX" address="auxregs:0860"/>
|
||||
<symbol name="DES_AUX" address="auxregs:0864"/>
|
||||
<symbol name="AP_AMV0" address="auxregs:0880"/>
|
||||
<symbol name="AP_AMM0" address="auxregs:0884"/>
|
||||
<symbol name="AP_AC0" address="auxregs:0888"/>
|
||||
<symbol name="AP_AMV1" address="auxregs:088C"/>
|
||||
<symbol name="AP_AMM1" address="auxregs:0890"/>
|
||||
<symbol name="AP_AC1" address="auxregs:0894"/>
|
||||
<symbol name="AP_AMV2" address="auxregs:0898"/>
|
||||
<symbol name="AP_AMM2" address="auxregs:089C"/>
|
||||
<symbol name="AP_AC2" address="auxregs:08A0"/>
|
||||
<symbol name="AP_AMV3" address="auxregs:08A4"/>
|
||||
<symbol name="AP_AMM3" address="auxregs:08A8"/>
|
||||
<symbol name="AP_AC3" address="auxregs:08AC"/>
|
||||
<symbol name="AP_AMV4" address="auxregs:08B0"/>
|
||||
<symbol name="AP_AMM4" address="auxregs:08B4"/>
|
||||
<symbol name="AP_AC4" address="auxregs:08B8"/>
|
||||
<symbol name="AP_AMV5" address="auxregs:08BC"/>
|
||||
<symbol name="AP_AMM5" address="auxregs:08C0"/>
|
||||
<symbol name="AP_AC5" address="auxregs:08C4"/>
|
||||
<symbol name="AP_AMV6" address="auxregs:08C8"/>
|
||||
<symbol name="AP_AMM6" address="auxregs:08CC"/>
|
||||
<symbol name="AP_AC6" address="auxregs:08D0"/>
|
||||
<symbol name="AP_AMV7" address="auxregs:08D4"/>
|
||||
<symbol name="AP_AMM7" address="auxregs:08D8"/>
|
||||
<symbol name="AP_AC7" address="auxregs:08DC"/>
|
||||
<symbol name="FPU_STATUS" address="auxregs:0C00"/>
|
||||
<symbol name="DPFP_1L" address="auxregs:0C04"/>
|
||||
<symbol name="DPFP_1H" address="auxregs:0C08"/>
|
||||
<symbol name="DPFP_2L" address="auxregs:0C0C"/>
|
||||
<symbol name="DPFP_2H" address="auxregs:0C10"/>
|
||||
<symbol name="DPFP_STATUS" address="auxregs:0C14"/>
|
||||
<symbol name="ERET" address="auxregs:1000"/>
|
||||
<symbol name="ERBTA" address="auxregs:1004"/>
|
||||
<symbol name="ERSTATUS" address="auxregs:1008"/>
|
||||
<symbol name="ECR" address="auxregs:100C"/>
|
||||
<symbol name="EFA" address="auxregs:1010"/>
|
||||
<symbol name="MMU_TLBPD0" address="auxregs:1014"/>
|
||||
<symbol name="MMU_TLBPD1" address="auxregs:1018"/>
|
||||
<symbol name="MMU_TLBINDEX" address="auxregs:101C"/>
|
||||
<symbol name="MMU_TLBCOMMAND" address="auxregs:1020"/>
|
||||
<symbol name="MMU_PID_and_MPUEN" address="auxregs:1024"/>
|
||||
<symbol name="ICAUSE1" address="auxregs:1028"/>
|
||||
<symbol name="ICAUSE2" address="auxregs:102C"/>
|
||||
<symbol name="AUX_IENABLE" address="auxregs:1030"/>
|
||||
<symbol name="AUX_ITRIGGER" address="auxregs:1034"/>
|
||||
<symbol name="XPU" address="auxregs:1040"/>
|
||||
<symbol name="BTA" address="auxregs:1048"/>
|
||||
<symbol name="BTA_L1" address="auxregs:104C"/>
|
||||
<symbol name="BTA_L2" address="auxregs:1050"/>
|
||||
<symbol name="AUX_IRQ_PULSE_CANCEL" address="auxregs:1054"/>
|
||||
<symbol name="AUX_IRQ_PENDING" address="auxregs:1058"/>
|
||||
<symbol name="MMU_SCRATCH_DATA0" address="auxregs:1060"/>
|
||||
<symbol name="MPUIC" address="auxregs:1080"/>
|
||||
<symbol name="MPUFA" address="auxregs:1084"/>
|
||||
<symbol name="MPURDB0" address="auxregs:1088"/>
|
||||
<symbol name="MPURDP0" address="auxregs:108C"/>
|
||||
<symbol name="MPURDB1" address="auxregs:1090"/>
|
||||
<symbol name="MPURDP1" address="auxregs:1094"/>
|
||||
<symbol name="MPURDB2" address="auxregs:1098"/>
|
||||
<symbol name="MPURDP2" address="auxregs:109C"/>
|
||||
<symbol name="MPURDB3" address="auxregs:10A0"/>
|
||||
<symbol name="MPURDP3" address="auxregs:10A4"/>
|
||||
<symbol name="MPURDB4" address="auxregs:10A8"/>
|
||||
<symbol name="MPURDP4" address="auxregs:10AC"/>
|
||||
<symbol name="MPURDB5" address="auxregs:10B0"/>
|
||||
<symbol name="MPURDP5" address="auxregs:10B4"/>
|
||||
<symbol name="MPURDB6" address="auxregs:10B8"/>
|
||||
<symbol name="MPURDP6" address="auxregs:10BC"/>
|
||||
<symbol name="MPURDB7" address="auxregs:10C0"/>
|
||||
<symbol name="MPURDP7" address="auxregs:10C4"/>
|
||||
<symbol name="MPURDB8" address="auxregs:10C8"/>
|
||||
<symbol name="MPURDP8" address="auxregs:10CC"/>
|
||||
<symbol name="MPURDB9" address="auxregs:10D0"/>
|
||||
<symbol name="MPURDP9" address="auxregs:10D4"/>
|
||||
<symbol name="MPURDB10" address="auxregs:10D8"/>
|
||||
<symbol name="MPURDP10" address="auxregs:10DC"/>
|
||||
<symbol name="MPURDB11" address="auxregs:10E0"/>
|
||||
<symbol name="MPURDP11" address="auxregs:10E4"/>
|
||||
<symbol name="MPURDB12" address="auxregs:10E8"/>
|
||||
<symbol name="MPURDP12" address="auxregs:10EC"/>
|
||||
<symbol name="MPURDB13" address="auxregs:10F0"/>
|
||||
<symbol name="MPURDP13" address="auxregs:10F4"/>
|
||||
<symbol name="MPURDB14" address="auxregs:10F8"/>
|
||||
<symbol name="MPURDP14" address="auxregs:10FC"/>
|
||||
<symbol name="MPURDB15" address="auxregs:1100"/>
|
||||
<symbol name="MPURDP15" address="auxregs:1104"/>
|
||||
<symbol name="PM_STATUS" address="auxregs:1140"/>
|
||||
<symbol name="WAKE" address="auxregs:1144"/>
|
||||
<symbol name="DVFS_PERFORMANCE" address="auxregs:1148"/>
|
||||
<symbol name="PWR_CTRL" address="auxregs:114C"/>
|
||||
<symbol name="LPB_CTRL" address="auxregs:1220"/>
|
||||
<symbol name="SMART_CONTROL" address="auxregs:1C00"/>
|
||||
</default_symbols>
|
||||
</processor_spec>
|
||||
2332
Ghidra/Processors/ARC/data/languages/ARCompact.slaspec
Normal file
2332
Ghidra/Processors/ARC/data/languages/ARCompact.slaspec
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,68 @@
|
||||
package ghidra.program.emulation;
|
||||
|
||||
import ghidra.pcode.emulate.Emulate;
|
||||
import ghidra.pcode.emulate.EmulateInstructionStateModifier;
|
||||
import ghidra.pcode.emulate.callother.OpBehaviorOther;
|
||||
import ghidra.pcode.memstate.MemoryState;
|
||||
import ghidra.pcodeCPort.error.LowlevelError;
|
||||
import ghidra.program.model.pcode.Varnode;
|
||||
|
||||
public class ARCompactEmulateInstructionStateModifier extends EmulateInstructionStateModifier {
|
||||
|
||||
public ARCompactEmulateInstructionStateModifier(Emulate emu) {
|
||||
super(emu);
|
||||
|
||||
registerPcodeOpBehavior("norm", new ARCompactNormOpBehavior());
|
||||
}
|
||||
|
||||
/**
|
||||
* Implements ARCompact's norm instruction.
|
||||
*
|
||||
* It is defined by:
|
||||
* Computes the normalization integer for the signed value in the
|
||||
* operand. The normalization integer is the amount by which the
|
||||
* operand must be shifted left to normalize the operand as a
|
||||
* 32-bit signed integer.
|
||||
*
|
||||
* An other way to understand this operation is to use some rules:
|
||||
* * norm(0) = 31
|
||||
* * if x s> 0, norm(x) = clz(x) - 1, with clz being "count leading zeros"
|
||||
* * if x s< 0, norm(x) = norm(~x)
|
||||
*/
|
||||
private class ARCompactNormOpBehavior implements OpBehaviorOther {
|
||||
@Override
|
||||
public void evaluate(Emulate emu, Varnode out, Varnode[] inputs) {
|
||||
if (out == null) {
|
||||
throw new LowlevelError("CALLOTHER: Norm op missing required output");
|
||||
}
|
||||
|
||||
if (inputs.length != 2 || inputs[1].getSize() == 0 || inputs[1].isConstant()) {
|
||||
throw new LowlevelError(
|
||||
"CALLOTHER: Norm op requires one non-constant varnode input");
|
||||
}
|
||||
|
||||
Varnode in = inputs[1];
|
||||
if (in.getSize() != 4 ) {
|
||||
throw new LowlevelError(
|
||||
"CALLOTHER: Norm op only supports varnodes of size 4 bytes");
|
||||
}
|
||||
|
||||
MemoryState memoryState = emu.getMemoryState();
|
||||
long value = memoryState.getValue(in);
|
||||
long mask = 1L << ((in.getSize() * 8) - 1);
|
||||
if ((mask & value) != 0) {
|
||||
value = ~value;
|
||||
}
|
||||
mask >>>= 1;
|
||||
long count = 0;
|
||||
while (mask != 0) {
|
||||
if ((mask & value) != 0) {
|
||||
break;
|
||||
}
|
||||
++count;
|
||||
mask >>>= 1;
|
||||
}
|
||||
memoryState.setValue(out, count);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class ARC700_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "ARCompact:LE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public ARC700_O0_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "ARC700_GCC_O0";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(ARC700_O0_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class ARC700_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "ARCompact:LE:32:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public ARC700_O3_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "ARC700_GCC_O3";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(ARC700_O3_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user