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x86: Export computed address as temporary instead of a varnode reference.

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Sleigh-InSPECtor 2024-05-20 15:22:52 +09:30
parent 3e34ab4932
commit 59a81fc4d3
1 changed files with 12 additions and 12 deletions
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24
Ghidra/Processors/x86/data/languages/ia.sinc
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@ -705,24 +705,24 @@ addr16: [BP + imm16] is mod=2 & r_m=6 & BP; imm16 { local tmp=BP+imm16;
addr16: [BX + imm16] is mod=2 & r_m=7 & BX; imm16 { local tmp=BX+imm16; export tmp; }
# 32-bit addressing modes (the offset portion)
addr32: [Rmr32] is mod=0 & Rmr32 { export Rmr32; }
addr32: [Rmr32] is mod=0 & Rmr32 { local tmp=Rmr32; export tmp; }
addr32: [Rmr32 + simm8_32] is mod=1 & Rmr32; simm8_32 { local tmp=Rmr32+simm8_32; export tmp; }
addr32: [Rmr32] is mod=1 & r_m!=4 & Rmr32; simm8=0 { export Rmr32; }
addr32: [Rmr32] is mod=1 & r_m!=4 & Rmr32; simm8=0 { local tmp=Rmr32; export tmp; }
addr32: [Rmr32 + imm32] is mod=2 & Rmr32; imm32 { local tmp=Rmr32+imm32; export tmp; }
addr32: [Rmr32] is mod=2 & r_m!=4 & Rmr32; imm32=0 { export Rmr32; }
addr32: [Rmr32] is mod=2 & r_m!=4 & Rmr32; imm32=0 { local tmp=Rmr32; export tmp; }
addr32: [imm32] is mod=0 & r_m=5; imm32 { export *[const]:4 imm32; }
addr32: [Base + Index*ss] is mod=0 & r_m=4; Index & Base & ss { local tmp=Base+Index*ss; export tmp; }
addr32: [Base] is mod=0 & r_m=4; index=4 & Base { export Base; }
addr32: [Base] is mod=0 & r_m=4; index=4 & Base { local tmp=Base; export tmp; }
addr32: [Index*ss + imm32] is mod=0 & r_m=4; Index & base=5 & ss; imm32 { local tmp=imm32+Index*ss; export tmp; }
addr32: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:4 imm32; }
addr32: [Base + Index*ss + simm8_32] is mod=1 & r_m=4; Index & Base & ss; simm8_32 { local tmp=simm8_32+Base+Index*ss; export tmp; }
addr32: [Base + simm8_32] is mod=1 & r_m=4; index=4 & Base; simm8_32 { local tmp=simm8_32+Base; export tmp; }
addr32: [Base + Index*ss] is mod=1 & r_m=4; Index & Base & ss; simm8=0 { local tmp=Base+Index*ss; export tmp; }
addr32: [Base] is mod=1 & r_m=4; index=4 & Base; simm8=0 { export Base; }
addr32: [Base] is mod=1 & r_m=4; index=4 & Base; simm8=0 { local tmp=Base; export tmp; }
addr32: [Base + Index*ss + imm32] is mod=2 & r_m=4; Index & Base & ss; imm32 { local tmp=imm32+Base+Index*ss; export tmp; }
addr32: [Base + imm32] is mod=2 & r_m=4; index=4 & Base; imm32 { local tmp=imm32+Base; export tmp; }
addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { local tmp=Base+Index*ss; export tmp; }
addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; }
addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { local tmp=Base; export tmp; }
@ifdef IA64
addr32: [pcRelSimm32] is bit64=1 & mod=0 & r_m=4; index=4 & base=5; pcRelSimm32 { export *[const]:4 pcRelSimm32; }
@ -735,14 +735,14 @@ Addr32_64: addr32 is addr32 { tmp:8 = sext(addr32); export tmp; }
# 64-bit addressing modes (the offset portion)
@ifdef IA64
addr64: [Rmr64] is mod=0 & Rmr64 { export Rmr64; }
addr64: [Rmr64] is mod=0 & Rmr64 { local tmp=Rmr64; export tmp; }
addr64: [Rmr64 + simm8_64] is mod=1 & Rmr64; simm8_64 { local tmp=Rmr64+simm8_64; export tmp; }
addr64: [Rmr64 + simm32_64] is mod=2 & Rmr64; simm32_64 { local tmp=Rmr64+simm32_64; export tmp; }
addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; }
addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; }
addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { local tmp=Rmr64; export tmp; }
addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { local tmp=Rmr64; export tmp; }
addr64: [pcRelSimm32] is mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; }
addr64: [Base64 + Index64*ss] is mod=0 & r_m=4; Index64 & Base64 & ss { local tmp=Base64+Index64*ss; export tmp; }
addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; }
addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { local tmp = Base64; export tmp; }
addr64: [simm32_64 + Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { local tmp=simm32_64+Index64*ss; export tmp; }
addr64: [Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0 { local tmp=Index64*ss; export tmp; }
addr64: [simm32_64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64 { export *[const]:8 simm32_64; }
@ -750,7 +750,7 @@ addr64: [Base64 + simm8_64] is mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base
addr64: [Base64 + Index64*ss + simm8_64] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64 { local tmp=simm8_64+Base64+Index64*ss; export tmp; }
addr64: [Base64 + Index64*ss] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0 { local tmp=Base64+Index64*ss; export tmp; }
addr64: [Base64 + simm32_64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64 { local tmp=simm32_64+Base64; export tmp; }
addr64: [Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { export Base64; }
addr64: [Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { local tmp = Base64; export tmp; }
addr64: [Base64 + Index64*ss + simm32_64] is mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64 { local tmp=simm32_64+Base64+Index64*ss; export tmp; }
addr64: [Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0 { local tmp=Base64+Index64*ss; export tmp; }
@endif
@ -4048,8 +4048,8 @@ macro xadd(dst,src) {
local tmp = dst;
addflags(tmp,src);
local result = tmp + src;
dst = result;
src = tmp;
dst = result;
resultflags(result);
}