From 5028d3015d72d366ae25bbf46decbab31dfc1a72 Mon Sep 17 00:00:00 2001
From: mumbel <mumbel@localhost.localdomain>
Date: Fri, 5 Apr 2019 22:07:30 -0500
Subject: [PATCH] ARM and THUMB corrections

ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)

ARM's CLREX matches THUMB's BL<c> <label>.  Added AMODE check to
CLREX
---
 .../Processors/ARM/data/languages/ARMTHUMBinstructions.sinc   | 2 +-
 Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc     | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
index 48a2d6a29f..51abf6007c 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
@@ -1103,7 +1103,7 @@ with : ARMcondCk=1 {
   resflags(Rd0811);
 }
 
-:add^thSBIT_CZNO^ItCond^".w"	Rd0811,sp,thshift2 		is TMode=1 & ItCond & op11=0x1e & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2
+:add^thSBIT_CZNO^ItCond^".w"	Rd0811,sp,thshift2 		is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2
 {
   build ItCond;
   build thshift2;
diff --git a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
index 26788139dc..c71d393967 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
@@ -2339,9 +2339,9 @@ ArmPCRelImmed12: reloff		is U23=0 & immed & rotate
   coprocessor_function(t_cpn,t_op1,t_op2,CRd,CRn,CRm);
 }
 
-@if defined(VERSION_6K)
+@if defined(VERSION_6K) || defined(VERSION_7)
 
-:clrex	is c0031=0xf57ff01f	{
+:clrex	is $(AMODE) & c0031=0xf57ff01f	{
 	ClearExclusiveLocal();
 }