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ARM and THUMB corrections

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ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)

ARM's CLREX matches THUMB's BL<c> <label>.  Added AMODE check to
CLREX
This commit is contained in:
mumbel 2019-04-05 22:07:30 -05:00
parent 49c2010b63
commit 5028d3015d
2 changed files with 3 additions and 3 deletions
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2
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
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@ -1103,7 +1103,7 @@ with : ARMcondCk=1 {
resflags(Rd0811);
}
:add^thSBIT_CZNO^ItCond^".w" Rd0811,sp,thshift2 is TMode=1 & ItCond & op11=0x1e & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2
:add^thSBIT_CZNO^ItCond^".w" Rd0811,sp,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2
{
build ItCond;
build thshift2;

4
Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
View File

@ -2339,9 +2339,9 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate
coprocessor_function(t_cpn,t_op1,t_op2,CRd,CRn,CRm);
}
@if defined(VERSION_6K)
@if defined(VERSION_6K) || defined(VERSION_7)
:clrex is c0031=0xf57ff01f {
:clrex is $(AMODE) & c0031=0xf57ff01f {
ClearExclusiveLocal();
}