mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2024-11-10 06:02:09 +00:00
SPARC: Various changes
- additional patterns - minor instruction fixes in mul/div/64-bit math - do not pass g0 to zeroflags - conditional trap
This commit is contained in:
mumbel
parent
c8a455e197
commit
34e1329595
@ -492,8 +492,9 @@ macro unpackflags(ccr) {
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:addcc RS1,regorimm,RD is op=2 & RD & op3=0x10 & RS1 & regorimm
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{
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addflags(RS1,regorimm);
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RD = RS1 + regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 + regorimm;
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zeroflags(res);
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RD = res;
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}
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:addc RS1,regorimm,RD is op=2 & RD & op3=0x8 & RS1 & regorimm {RD = RS1 + regorimm + zext(i_cf);}
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@ -502,8 +503,9 @@ macro unpackflags(ccr) {
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{
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local original_i_cf:$(SIZE) = zext(i_cf);
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addCarryFlags(RS1,regorimm);
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RD = RS1 + regorimm + original_i_cf;
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zeroflags(RD);
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local res:$(SIZE) = RS1 + regorimm + original_i_cf;
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zeroflags(res);
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RD = res;
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}
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#-----------------------
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:and RS1,regorimm,RD is op=2 & RD & op3=0x1 & RS1 & regorimm {RD = RS1 & regorimm;}
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@ -511,16 +513,18 @@ macro unpackflags(ccr) {
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:andcc RS1,regorimm,RD is op=2 & RD & op3=0x11 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 & regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 & regorimm;
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zeroflags(res);
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RD = res;
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}
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:andn RS1,regorimm,RD is op=2 & RD & op3=0x5 & RS1 & regorimm {RD = RS1 & ~regorimm;}
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:andncc RS1,regorimm,RD is op=2 & RD & op3=0x15 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 & ~regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 & ~regorimm;
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zeroflags(res);
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RD = res;
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}
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:or RS1,regorimm,RD is op=2 & RD & op3=0x2 & RS1 & regorimm {RD = RS1 | regorimm;}
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@ -528,24 +532,27 @@ macro unpackflags(ccr) {
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:orcc RS1,regorimm,RD is op=2 & RD & op3=0x12 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 | regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 | regorimm;
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zeroflags(res);
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RD = res;
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}
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:orn RS1,regorimm,RD is op=2 & RD & op3=0x6 & RS1 & regorimm {RD = RS1 | ~regorimm;}
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:orncc RS1,regorimm,RD is op=2 & RD & op3=0x16 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 | ~regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 | ~regorimm;
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zeroflags(res);
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RD = res;
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}
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:xor RS1,regorimm,RD is op=2 & RD & op3=0x3 & RS1 & regorimm {RD = RS1 ^ regorimm;}
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:xorcc RS1,regorimm,RD is op=2 & RD & op3=0x13 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 ^ regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 ^ regorimm;
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zeroflags(res);
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RD = res;
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}
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:xnor RS1,regorimm,RD is op=2 & RD & op3=0x7 & RS1 & regorimm {RD = RS1 ^ ~regorimm;}
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@ -553,8 +560,9 @@ macro unpackflags(ccr) {
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:xnorcc RS1,regorimm,RD is op=2 & RD & op3=0x17 & RS1 & regorimm
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{
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logicflags();
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RD = RS1 ^ ~regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 ^ ~regorimm;
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zeroflags(res);
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RD = res;
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}
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# ---------------
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@ -615,8 +623,9 @@ macro unpackflags(ccr) {
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:subcc RS1,regorimm,RD is op=2 & RD & op3=0x14 & RS1 & regorimm
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{
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subflags(RS1,regorimm);
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RD = RS1 - regorimm;
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zeroflags(RD);
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local res:$(SIZE) = RS1 - regorimm;
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zeroflags(res);
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RD = res;
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}
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:subc RS1,regorimm,RD is op=2 & RD & op3=0xc & RS1 & regorimm
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@ -628,8 +637,9 @@ macro unpackflags(ccr) {
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{
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local original_cf:$(SIZE) = zext(i_cf);
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subCarryFlags(RS1,regorimm);
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RD = RS1 - regorimm - original_cf;
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zeroflags(RD);
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local res:$(SIZE) = RS1 - regorimm - original_cf;
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zeroflags(res);
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RD = res;
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}
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# ---------------
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@ -641,8 +651,8 @@ macro unpackflags(ccr) {
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:cmp RS1,regorimm is op=0x2 & rd=0x0 & op3=0x14 & RS1 & regorimm
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{
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subflags(RS1,regorimm);
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local tmp = RS1 - regorimm;
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zeroflags(tmp);
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local res:$(SIZE) = RS1 - regorimm;
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zeroflags(res);
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}
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@ -825,43 +835,65 @@ callreloff: reloc is disp30 [reloc=inst_start+4*disp30;] { export *:$(SIZE) rel
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#----------------MULTIPLY 32 bit
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@if SIZE=="8"
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:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm {RD = zext(RS1:4) * zext(regorimm:4); Y=RD>>32;}
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:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm {RD = sext(RS1:4) * sext(regorimm:4); Y=RD>>32;}
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:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm {RD = zext(RS1:4) * zext(regorimm:4); Y=RD>>32; zeroflags(RD); logicflags();}
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:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm {RD = sext(RS1:4) * sext(regorimm:4); Y=RD>>32; zeroflags(RD); logicflags();}
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:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm
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{
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local res:8 = zext(RS1:4) * zext(regorimm:4);
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Y = res >> 32;
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RD = res:4;
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}
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:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm
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{
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local res:8 = sext(RS1:4) * sext(regorimm:4);
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Y = res s>> 32;
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RD = res:4;
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}
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:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm
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{
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local res:8 = zext(RS1:4) * zext(regorimm:4);
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Y = res >> 32;
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zeroflags(res:4);
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RD = res:4;
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logicflags();
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}
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:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm
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{
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local res:8 = sext(RS1:4) * sext(regorimm:4);
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Y = res s>> 32;
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zeroflags(res:4);
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RD = res:4;
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logicflags();
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}
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@else
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# size = 4
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:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm
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:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm
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{
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tmp_RS1:8 = zext(RS1);
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tmp_regorimm:8 = zext(regorimm);
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tmp:8 = tmp_RS1 * tmp_regorimm;
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RD = tmp:4; tmp2:8 = tmp >> 32;
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Y = tmp2:4;
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local res:8 = zext(RS1:4) * zext(regorimm:4);
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Y = res[32,32];
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RD = res:4;
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}
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:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm
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:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm
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{
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tmp_RS1:8 = sext(RS1);
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tmp_regorimm:8 = sext(regorimm);
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tmp:8 = tmp_RS1 * tmp_regorimm;
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RD = tmp:4; tmp2:8 = tmp >> 32;
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Y = tmp2:4;
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local res:8 = sext(RS1:4) * sext(regorimm:4);
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Y = res[32,32];
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RD = res:4;
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}
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:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm
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:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm
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{
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RD = zext(RS1:4) * zext(regorimm:4);
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Y=RD>>32;
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zeroflags(RD);
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local res:8 = zext(RS1:4) * zext(regorimm:4);
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Y = res[32,32];
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zeroflags(res:4);
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RD = res:4;
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logicflags();
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}
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:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm
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:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm
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{
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RD = zext(RS1:4) * zext(regorimm:4);
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Y=RD>>32;
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zeroflags(RD);
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local res:8 = sext(RS1:4) * sext(regorimm:4);
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Y = res[32,32];
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zeroflags(res:4);
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RD = res:4;
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logicflags();
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}
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@ -869,7 +901,7 @@ callreloff: reloc is disp30 [reloc=inst_start+4*disp30;] { export *:$(SIZE) rel
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#----------------MULTIPLY Step
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:mulscc RS1,regorimm,RD is op=2 & RD & op3=0x24 & RS1 & regorimm
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:mulscc RS1,regorimm,RD is op=2 & RD & op3=0x24 & RS1 & regorimm
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{
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local ccr:4 = zext(i_nf ^^ i_vf);
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ccr = ccr << 31;
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@ -883,48 +915,53 @@ callreloff: reloc is disp30 [reloc=inst_start+4*disp30;] { export *:$(SIZE) rel
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addflags32(addend,shifted);
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#upper 32 bits of RD are undefined according to the manual
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local tbit:4 = (RS1:4 & 0x1:4) << 31;
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RD = zext(sum);
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zeroflags(RD);
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local res:$(SIZE) = zext(sum);
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zeroflags(res);
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RD = res;
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#Y is 64 bits in Sparc 9 but the high 32 are fixed to 0
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Y = zext((Y:4 >> 1:4) | tbit);
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}
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#----------------DIVIDE (64-bit / 32-bit)
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# NB- Beware, the plus + operator has higher precedence than shift <<
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# (These are Java rules. C rules have shift and + at the same level, so left to right)
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:udiv RS1,regorimm,RD is op=2 & RD & op3=0x0e & RS1 & regorimm
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:udiv RS1,regorimm,RD is op=2 & RD & op3=0x0e & RS1 & regorimm
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{
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numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff);
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denom:$(SIZE) = regorimm & 0xffffffff;
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RD = numerator / denom;
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numerator:8 = (zext(Y) << 32) + zext(RS1);
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denom:8 = zext(regorimm:4);
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local res:8 = numerator / denom;
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RD = zext(res:4);
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}
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:sdiv RS1,regorimm,RD is op=2 & RD & op3=0x0f & RS1 & regorimm
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:sdiv RS1,regorimm,RD is op=2 & RD & op3=0x0f & RS1 & regorimm
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{
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numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff);
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denom:$(SIZE) = regorimm & 0xffffffff;
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RD = numerator s/ denom;
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}
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numerator:8 = (sext(Y) << 32) + zext(RS1:4);
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denom:8 = sext(regorimm:4);
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local res:8 = numerator s/ denom;
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RD = sext(res:4);
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}
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:udivcc RS1,regorimm,RD is op=2 & RD & op3=0x1e & RS1 & regorimm
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:udivcc RS1,regorimm,RD is op=2 & RD & op3=0x1e & RS1 & regorimm
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{
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numerator:$(SIZE)= ( Y << 32) + (RS1 & 0xffffffff);
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denom:$(SIZE) = regorimm & 0xffffffff;
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RD = numerator / denom;
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zeroflags(RD);
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i_vf = RD > 0xffffffff;
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numerator:8 = (zext(Y) << 32) + zext(RS1:4);
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denom:8 = zext(regorimm:4);
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local res:8 = numerator / denom;
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zeroflags(res:4);
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RD = zext(res:4);
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i_vf = res > 0xffffffff;
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i_cf = 0;
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x_vf = 0;
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x_cf = 0;
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}
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:sdivcc RS1,regorimm,RD is op=2 & RD & op3=0x1f & RS1 & regorimm
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:sdivcc RS1,regorimm,RD is op=2 & RD & op3=0x1f & RS1 & regorimm
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{
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numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff);
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denom:$(SIZE) = regorimm & 0xffffffff;
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RD = numerator s/ denom;
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zeroflags(RD);
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i_vf = (RD s>= 0x80000000) || (RD s<= -0x7fffffff);
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numerator:8 = (sext(Y) << 32) + (zext(RS1) & 0xffffffff);
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denom:8 = sext(regorimm:4);
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local res:8 = numerator s/ denom;
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zeroflags(res:4);
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RD = sext(res:4);
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i_vf = (res s>= 0x80000000) || (res s<= -0x7ffffffff);
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i_cf = 0;
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x_vf = 0;
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x_cf = 0;
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@ -990,6 +1027,12 @@ sethidisp: "%hi("^hi^")" is udisp22 [hi=udisp22<<10;] { export *[const]:$(SIZE)
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:restore RS1,regorimm,RD is op=0x2 & RD & op3=0x3d & RS1 & regorimm { local tmp = RS1 + regorimm; restore(); didrestore=1; RD = tmp; }
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:restore is op=0x2 & rd=0 & op3=0x3d { restore(); didrestore=1; }
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# FIXME 'jmpl' can have 'return' in the delayslot to return from a user trap handler
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# - jmpl sets the trapped PC supplied to user trap handler
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# - return sets the trapped nPC supplied to user trap handler
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# Nothing in instruction encoding defines this, requiring a context register;
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# or a fake 8-byte instruction, requiring logic for 64-bits of tokens
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:return retea is op=0x2 & op3=0x39 & retea { build retea; restore(); delayslot(1); didrestore=1; return [retea]; }
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:jmpl retea,RD is op=0x2 & RD & op3=0x38 & retea { build retea; RD = inst_start; delayslot(1); goto [retea]; }
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@ -1010,55 +1053,73 @@ sethidisp: "%hi("^hi^")" is udisp22 [hi=udisp22<<10;] { export *[const]:$(SIZE)
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casa_ea: [RS1]imm_asi is i=0 & RS1 & imm_asi { local tmp1:1 = imm_asi; local tmp = RS1+segment(tmp1); export tmp; }
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casa_ea: [RS1]%ASI is i=1 & RS1 & ASI { local tmp = RS1+segment(ASI); export tmp; }
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:casa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3c & casa_ea & RS2
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{
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local tmp:4=RD:4;
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RD=zext(*:4 casa_ea);
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if ((RS2 & 0xFFFFFFFF)!=RD) goto <end>;
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*:4 casa_ea=tmp;
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:casa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3c & casa_ea & RS2
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{
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local tmp:4=RD:4;
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local tmp2:$(SIZE) = RS2;
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local tmp_ea:$(SIZE) = casa_ea;
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RD=zext(*:4 tmp_ea);
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if ((tmp2 & 0xFFFFFFFF)!=RD) goto <end>;
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*:4 tmp_ea=tmp;
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<end>
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}
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:casxa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3e & casa_ea & RS2
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{
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local tmp=RD;
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RD=*:$(SIZE) casa_ea;
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if (RS2!=RD) goto <end>;
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*:$(SIZE) casa_ea=tmp;
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:casxa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3e & casa_ea & RS2
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{
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local tmp=RD;
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local tmp2:$(SIZE) = RS2;
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local tmp_ea:$(SIZE) = casa_ea;
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RD=*:$(SIZE) tmp_ea;
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if (tmp2!=RD) goto <end>;
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*:$(SIZE) tmp_ea=tmp;
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<end>
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}
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:impdef1 is op=0x2 & op3=0x36 unimpl
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:impdef2 is op=0x2 & op3=0x37 unimpl
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:ldstub ea,RD is op=0x3 & RD & op3=0xd & ea { RD = zext(*:1 ea); *:1 ea = 0xFF; }
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:ldstuba ea_alt,RD is op=0x3 & RD & op3=0x1d & ea_alt { RD = zext(*:1 ea_alt); *:1 ea_alt = 0xFF; }
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:ldstub ea,RD is op=0x3 & RD & op3=0xd & ea
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{
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local tmp_ea:$(SIZE) = ea;
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RD = zext(*:1 tmp_ea);
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*:1 tmp_ea = 0xFF;
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}
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:ldstuba ea_alt,RD is op=0x3 & RD & op3=0x1d & ea_alt
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{
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local tmp_ea:$(SIZE) = ea_alt;
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RD = zext(*:1 tmp_ea);
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*:1 tmp_ea = 0xFF;
|
||||
}
|
||||
|
||||
:swap ea,RD is op=0x3 & RD & op3=0xF & ea { tmp:4=RD:4; RD = zext(*:4 ea); *:4 ea = tmp; }
|
||||
:swapa ea_alt,RD is op=0x3 & RD & op3=0x1F & ea_alt { tmp:4=RD:4; RD = zext(*:4 ea_alt); *:4 ea_alt = tmp; }
|
||||
:swap ea,RD is op=0x3 & RD & op3=0xF & ea { local tmp_ea:$(SIZE) = ea; tmp:4=RD:4; RD = zext(*:4 tmp_ea); *:4 tmp_ea = tmp; }
|
||||
:swapa ea_alt,RD is op=0x3 & RD & op3=0x1F & ea_alt { local tmp_ea:$(SIZE) = ea_alt; tmp:4=RD:4; RD = zext(*:4 tmp_ea); *:4 tmp_ea = tmp; }
|
||||
|
||||
:taddcc RS1,regorimm,RD is op=2 & RD & op3=0x20 & RS1 & regorimm
|
||||
:taddcc RS1,regorimm,RD is op=2 & RD & op3=0x20 & RS1 & regorimm
|
||||
{
|
||||
taddflags(RS1,regorimm);
|
||||
RD = RS1 + regorimm;
|
||||
zeroflags(RD);
|
||||
local res:$(SIZE) = RS1 + regorimm;
|
||||
zeroflags(res);
|
||||
RD = res;
|
||||
}
|
||||
:taddcctv RS1,regorimm,RD is op=2 & RD & op3=0x22 & RS1 & regorimm
|
||||
:taddcctv RS1,regorimm,RD is op=2 & RD & op3=0x22 & RS1 & regorimm
|
||||
{
|
||||
taddflags(RS1,regorimm);
|
||||
RD = RS1 + regorimm;
|
||||
zeroflags(RD);
|
||||
local res:$(SIZE) = RS1 + regorimm;
|
||||
zeroflags(res);
|
||||
RD = res;
|
||||
}
|
||||
:tsubcc RS1,regorimm,RD is op=2 & RD & op3=0x21 & RS1 & regorimm
|
||||
:tsubcc RS1,regorimm,RD is op=2 & RD & op3=0x21 & RS1 & regorimm
|
||||
{
|
||||
tsubflags(RS1,regorimm);
|
||||
RD = RS1 - regorimm;
|
||||
zeroflags(RD);
|
||||
local res:$(SIZE) = RS1 - regorimm;
|
||||
zeroflags(res);
|
||||
RD = res;
|
||||
}
|
||||
:tsubcctv RS1,regorimm,RD is op=2 & RD & op3=0x23 & RS1 & regorimm
|
||||
:tsubcctv RS1,regorimm,RD is op=2 & RD & op3=0x23 & RS1 & regorimm
|
||||
{
|
||||
tsubflags(RS1,regorimm);
|
||||
RD = RS1 - regorimm;
|
||||
zeroflags(RD);
|
||||
local res:$(SIZE) = RS1 - regorimm;
|
||||
zeroflags(res);
|
||||
RD = res;
|
||||
}
|
||||
|
||||
tcc: icc is cc1_4=0 & cc0_4=0 & icc { export icc; }
|
||||
@ -1070,7 +1131,11 @@ TICC: "%xcc" is cc1_4=1 &cc0_4=0 { }
|
||||
trap: RS1+RS2 is i=0 & RS1 & RS2 { local tmp = ((RS1 + RS2) & 0x7F); export tmp; }
|
||||
trap: RS1+swtrap is i=1 & RS1 & swtrap { local tmp = ((RS1 + swtrap) & 0x7F); export tmp; }
|
||||
|
||||
:t^tcc TICC, trap is op=0x2 & op3=0x3a & tcc & TICC & trap { sw_trap(trap); }
|
||||
:t^tcc TICC, trap is op=0x2 & op3=0x3a & tcc & TICC & trap
|
||||
{
|
||||
if (!tcc) goto inst_next;
|
||||
sw_trap(trap);
|
||||
}
|
||||
|
||||
membar_mask: is cmask & mmask { tmp:1 = (cmask << 4) | mmask; export tmp; }
|
||||
|
||||
|
||||
@ -2,30 +2,21 @@
|
||||
<patternpairs totalbits="32" postbits="16">
|
||||
<prepatterns>
|
||||
<data>0x81f00000 </data> <!-- done -->
|
||||
<data>0x81c7e008 0x........ </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RET : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81c3e008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETL : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81cfe008 0x........ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 </data> <!-- RETURN : delayslot filler -->
|
||||
<data>0x81c7e008 0x........ </data> <!-- RET : delayslot -->
|
||||
<data>0x81c7e008 0x........ 0000000. 0x000000 </data> <!-- RET : delayslot filler/nop -->
|
||||
<data>0x81c3e008 0x........ </data> <!-- RETL : delayslot -->
|
||||
<data>0x81c3e008 0x........ 0000000. 0x000000 </data> <!-- RETL : delayslot filler/nop -->
|
||||
<data>0x81cfe008 0x........ </data> <!-- RETURN : delayslot -->
|
||||
<data>0x81cfe008 0x........ 0000000. 0x000000 </data> <!-- RETURN : delayslot filler/nop -->
|
||||
<data>0x10 101..... 0x.... 0x........ </data> <!-- BA -label : delayslot -->
|
||||
<data>0x10 101..... 0x.... 0x........ 0000000. 0x000000 </data> <!-- BA -label : delayslot filler/nop -->
|
||||
<data>0x30 101..... 0x.... </data> <!-- BA,A -label (no delayslot)-->
|
||||
<data>0x30 101..... 0x.... 0000000. 0x000000 </data> <!-- BA,A -label (no delayslot): filler/nop -->
|
||||
<data>01...... 0x...... 10.....1 11101... 0x.... </data> <!-- CALL label; RESTORE : filler/nop -->
|
||||
<data>01...... 0x...... 10.....1 11101... 0x.... 0000000. 0x000000 </data> <!-- CALL label; RESTORE : filler/nop -->
|
||||
<data>01...... 0x...... 0x9E 00010... 0x.... </data> <!-- CALL label; OR rs1,rs2,o7 : filler/nop -->
|
||||
<data>01...... 0x...... 0x9E 00010... 0x.... 0000000. 0x000000 </data> <!-- CALL label; OR rs1,rs2,o7 : filler/nop -->
|
||||
<data>0000000. 0x000000 0000000. 0x000000 </data> <!-- filler/nop -->
|
||||
</prepatterns>
|
||||
<postpatterns>
|
||||
<data>10011101 11100011 10111... ........</data> <!-- save sp, xx, sp -->
|
||||
|
||||
Loading…
Reference in New Issue
Block a user