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[NDS32] Add baseline v3
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Timothée COCAULT
parent
2e7dd784dc
commit
21c42371f2
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@ -53,6 +53,8 @@ define token instr32(32)
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Imm20u = (0, 19)
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Imm20s = (0, 19) signed
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Imm24s = (0, 23) signed
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Imm11s = (8, 18) signed
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Imm8s = (0, 7) signed
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sv = (8, 9)
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SrIdx = (10, 19)
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Swid = (5, 19)
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@ -86,6 +88,10 @@ define token instr32(32)
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GpSub2 = (18, 19)
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GpSub3 = (17, 19)
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sh = (5, 9)
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Bxxc = (19, 19)
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LsmwRa = (15, 19)
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LsmwRb = (20, 24)
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LsmwRb_ = (20, 24)
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@ -135,6 +141,7 @@ attach variables [Dthigh] [
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@define GPR "(Alu2Mod=0b0001)"
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@define BR1 "(Opc=0b100110)"
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@define BR2 "(Opc=0b100111)"
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@define BR3 "(Opc=0b101101)"
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@define LSMW "(Opc=0b011101)"
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@define JI "(Opc=0b100100)"
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@define MEM "(Opc=0b011100)"
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@ -620,6 +627,47 @@ GpWordAddress: [+ off] is Imm17s [ off = Imm17s << 2; ] { addr:4 = gp + off; exp
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@endif
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### 32-bit Baseline V3 instructions ###
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@if defined(BASELINE_V3)
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### ALU Instructions with Shift Operation (v3) ###
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:add_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00000 { Rt = Ra + (Rb << sh); }
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:and_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00010 { Rt = Ra & (Rb << sh); }
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:or_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00100 { Rt = Ra | (Rb << sh); }
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:sub_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00001 { Rt = Ra - (Rb << sh); }
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:xor_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00011 { Rt = Ra ^ (Rb << sh); }
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:add_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11100 { Rt = Ra + (Rb << sh); }
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:and_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11110 { Rt = Ra & (Rb << sh); }
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:or_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b10101 { Rt = Ra | (Rb << sh); }
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:sub_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11101 { Rt = Ra - (Rb << sh); }
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:xor_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11111 { Rt = Ra ^ (Rb << sh); }
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### Conditional Branch and Jump Instructions (V3) ###
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Rel8: addr is Imm8s [ addr = inst_start + (Imm8s << 1); ] { export *:4 addr; }
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:beqc Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=0 & Imm11s & Rel8 { if(Rt == Imm11s) goto Rel8; }
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:bnec Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=1 & Imm11s & Rel8 { if(Rt != Imm11s) goto Rel8; }
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:jralnez Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00011 { if(Rb == 0) goto <end>; Rt = inst_next; call [Rb]; <end> }
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:jrnez Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00010 { if(Rb == 0) goto <end>; goto [Rb]; <end> }
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### Bit Manipulation Instructions (V3) ###
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:bitc Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b10010 { Rt = Ra & (~Rb); }
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:bitci Rt, Ra, Imm15u is $(I32) & Opc=0b110011 & Rt & Ra & Imm15u { Rt = Ra & (~Imm15u); }
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### Cache Control Instruction (V3) ###
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# TODO: Add CCTL L1D_WBALL, level
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@endif
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### 32-bit ISA extension ###
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### ALU Instruction (Performance) ###
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@ -771,27 +819,36 @@ define token instr16(16)
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opc5 = (10, 14)
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opc6 = (9, 14)
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opc7 = (8, 14)
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opc8 = (7, 14)
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opc10 = (5, 14)
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re2 = (5, 6)
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rt5 = (5, 9)
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ra4 = (5, 8)
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rt4 = (5, 8)
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ra5 = (0, 4)
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rb5 = (0, 4)
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rt5b = (0, 4)
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rt3 = (6, 8)
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rt3b = (8, 10)
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ra3 = (3, 5)
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rb3 = (0, 2)
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imm3u = (0, 2)
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imm3ub = (3, 5)
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imm5u = (0, 4)
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imm5s = (0, 4) signed
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imm6u = (0, 5)
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imm7u = (0, 6)
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imm8s = (0, 7) signed
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imm10s = (0, 9) signed
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xwi37_ls = (7, 7)
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swid9 = (0, 8)
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rt5e1 = (4, 7)
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rt5e2 = (4, 7)
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ra5e1 = (0, 3)
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ra5e2 = (0, 3)
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;
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attach variables [rt5 ra5 rb5] [
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attach variables [rt5 ra5 rb5 rt5b] [
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a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp
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];
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@ -803,10 +860,23 @@ attach variables [rt3 ra3 rt3b rb3] [
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a0 a1 a2 a3 a4 a5 s0 s1
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];
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attach variables [ra5e1 rt5e1] [
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a0 a2 a4 s0 s2 s4 s6 s8 t0 t2 t4 t6 t8 p0 fp lp
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];
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attach variables [ra5e2 rt5e2] [
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a1 a3 a5 s1 s3 s5 s7 ta t1 t3 t5 t7 t9 p1 gp sp
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];
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attach variables [re2] [
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s0 s2 s4 s8
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];
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@define I16 "(opsz=1)"
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@define BFMI333 "(opc6=0b001011)"
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@define XWI37 "(opc4=0b0111)"
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@define XWI37SP "(opc4=0b1110)"
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@define MISC33 "(opc6=0b111111)"
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### Move Instruction ###
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@ -928,3 +998,84 @@ sp_rel7w: [+ rel7w] is rel7w { addr:4 = sp + rel7w; export addr; }
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@endif
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### 16-bit Baseline V3 instructions ###
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@if defined(BASELINE_V3)
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### ALU Instructions (V3 16-bit) ###
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imm6u_: imm8 is imm6u [ imm8 = imm6u << 2; ] { export *[const]:4 imm8; }
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:addri36.sp rt3, imm6u_ is $(I16) & opc6=0b011000 & rt3 & imm6u_ { rt3 = sp + imm6u_; }
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:add5.pc rt5b is $(I16) & opc10=0b1011101101 & rt5b { rt5b = pc + rt5b; }
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:and33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b110 { rt3 = rt3 & ra3; }
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:neg33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b010 { rt3 = -ra3; }
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:not33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b011 { rt3 = ~ra3; }
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:or33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b111 { rt3 = rt3 | ra3; }
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:xor33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b101 { rt3 = rt3 ^ ra3; }
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### Bit Manipulation Instructions (V3 16-bit) ###
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:bmski33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b110 { rt3 = (rt3 >> imm3ub) & 1; }
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:fexti33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b111 { rt3 = rt3 & ((1 << (imm3ub + 1)) - 1); }
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### Misc. Instructions (V3 16-bit) ###
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imm7n: off is imm5u [ off = -((32 - imm5u) << 2); ] { export *[const]:4 off; }
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:lwi45.fe rt4, [imm7n] is $(I16) & opc6=0b011001 & rt4 & imm7n { addr:4 = s2 + imm7n; rt4 = *addr; }
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:movd44 rt5e1, ra5e1 is $(I16) & opc7=0b1111101 & rt5e1 & rt5e2 & ra5e1 & ra5e2 { rt5e1 = ra5e1; rt5e2 = ra5e2; }
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imm5u_: imm6 is imm5u [ imm6 = imm5u + 16; ] { export *[const]:4 imm6; }
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:movpi45 rt4, imm5u_ is $(I16) & opc6=0b111101 & rt4 & imm5u_ { rt4 = imm5u_; }
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:mul33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b100 { rt3 = rt3 * ra3; }
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# Note: POP25 and PUSH25 are highly untested ! And they just look messy :/
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imm5u__: imm8 is imm5u [ imm8 = imm5u << 3; ] { export *[const]:4 imm8; }
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macro push25_special() { Smwad(lp); Smwad(gp); Smwad(fp); }
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macro push25_s0() { Smwad(s0); }
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macro push25_s2() { Smwad(s2); Smwad(s1); push25_s0(); }
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macro push25_s4() { Smwad(s4); Smwad(s3); push25_s2(); }
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macro push25_s8() { Smwad(s8); Smwad(s7); Smwad(s6); Smwad(s5); push25_s4(); }
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push25_re: re2 is re2 & re2=0 { push25_s0(); }
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push25_re: re2 is re2 & re2=1 { push25_s2(); }
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push25_re: re2 is re2 & re2=2 { push25_s4(); }
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push25_re: re2 is re2 & re2=3 { push25_s8(); }
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:push25 push25_re, imm5u__ is $(I16) & opc8=0b11111000 & re2 & push25_re & imm5u__ {
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mult_addr = sp;
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push25_special();
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build push25_re;
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sp = mult_addr - imm5u__;
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if(re2 < 1) goto <end>;
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s2 = pc & 0xfffffffc;
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<end>
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}
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macro pop25_special() { Lmwbi(fp); Lmwbi(gp); Lmwbi(lp); }
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macro pop25_s0() { Lmwbi(s0); }
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macro pop25_s2() { pop25_s0(); Lmwbi(s1); Lmwbi(s2); }
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macro pop25_s4() { pop25_s2(); Lmwbi(s3); Lmwbi(s4); }
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macro pop25_s8() { pop25_s4(); Lmwbi(s5); Lmwbi(s6); Lmwbi(s7); Lmwbi(s8); }
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pop25_re: re2 is re2 & re2=0 { pop25_s0(); }
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pop25_re: re2 is re2 & re2=1 { pop25_s2(); }
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pop25_re: re2 is re2 & re2=2 { pop25_s4(); }
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pop25_re: re2 is re2 & re2=3 { pop25_s8(); }
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:pop25 pop25_re, imm5u__ is $(I16) & opc8=0b11111001 & re2 & pop25_re & imm5u__ {
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mult_addr = sp;
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build pop25_re;
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pop25_special();
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sp = mult_addr + imm5u__;
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return [lp];
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}
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@endif
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@ -1,4 +1,5 @@
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@define BASELINE_V2 "yes"
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@define BASELINE_V3 "yes"
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@define PERFORMANCE_V1 "yes"
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@define PERFORMANCE_V2 "yes"
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@define ENDIAN "big"
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@ -1,4 +1,5 @@
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@define BASELINE_V2 "yes"
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@define BASELINE_V3 "yes"
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@define PERFORMANCE_V1 "yes"
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@define PERFORMANCE_V2 "yes"
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@define ENDIAN "little"
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