Nixyri/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2024-09-20 09:31:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/GP-4702_emteere_PPCPseudoOpDestAssignPPC' into patch

Browse Source
This commit is contained in:
Ryan Kurtz 2024-08-27 13:28:50 -04:00
commit 217b08c741
2 changed files with 36 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Ghidra/Processors/PowerPC/data/languages/SPE_APU.sinc
View File

@ -2654,8 +2654,8 @@ define pcodeop ROTL64;
define pcodeop VectorSplatFractionalImmediate;
:evsplatfi D,BU_SIMM is OP=4 & D & BU_SIMM & XOP_0_10=0x22B {
# TODO definition
# RT0:31 􀁉 SI || 270
# RT32:63 􀁉 SI || 270
# RT0:31 = SI || 270
# RT32:63 = SI || 270
# The value specified by SI is padded with trailing zeros
# and placed in both elements of RT. The SI ends up in
# bit positions RT0:4 and RT32:36.
@ -2687,9 +2687,9 @@ define pcodeop VectorSplatImmediate;
define pcodeop VectorShiftRightWordImmediateSigned;
:evsrwis D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x223 {
# TODO definition
# n 􀁉 UI
# RT0:31 􀁉 EXTS((RA)0:31-n)
# RT32:63 􀁉 EXTS((RA)32:63-n)
# n = UI
# RT0:31 = EXTS((RA)0:31-n)
# RT32:63 = EXTS((RA)32:63-n)
# Both high and low elements of RA are shifted right by
# the 5-bit UI value. Bits in the most significant positions
# vacated by the shift are filled with a copy of the sign bit.
@ -2703,9 +2703,9 @@ define pcodeop VectorShiftRightWordImmediateSigned;
define pcodeop VectorShiftRightWordImmediateUnsigned;
:evsrwiu D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x222 {
# TODO definition
# n 􀁉 UI
# RT0:31 􀁉 EXTZ((RA)0:31-n)
# RT32:63 􀁉 EXTZ((RA)32:63-n)
# n = UI
# RT0:31 = EXTZ((RA)0:31-n)
# RT32:63 = EXTZ((RA)32:63-n)
# Both high and low elements of RA are shifted right by
# the 5-bit UI value; zeros are shifted into the most significant
# position.

52
Ghidra/Processors/PowerPC/data/languages/evx.sinc
View File

@ -18,15 +18,19 @@ define pcodeop vectorShiftRightWordUnsigned;
vrD_64_0 = vrA_64_0 ^ vrB_64_0;
}
@if REGISTER_SIZE=="8"
:evmergehi S,A,B is OP=4 & S & A & B & XOP_0_10=556
{
vectorMergeHigh(S,A,B);
S[32,32] = A[32,32];
S[ 0,32] = B[ 0,32];
}
:evmergelo S,A,B is OP=4 & S & A & B & XOP_0_10=557
{
vectorMergeLow(S,A,B);
S[32,32] = A[0,32];
S[ 0,32] = B[0,32];
}
@endif
:evldd RT,dUI16PlusRAOrZeroAddress is OP=4 & RT & dUI16PlusRAOrZeroAddress & XOP_0_10=769
@ -41,19 +45,31 @@ define pcodeop vectorShiftRightWordUnsigned;
RT = *:8 ($(EATRUNC));
}
@if REGISTER_SIZE=="8"
@ifndef IS_ISA
:evsrws S,A,B is OP=4 & S & A & B & XOP_0_10=545
{
vectorShiftRightWordSigned(S,A,B);
local low:4 = A[0,32];
local high:4 = A[32,32];
local low_shift:1 = B[0,5];
local high_shift:1 = B[32,5];
S[0,32] = low s>> zext(low_shift);
S[32,32] = high s>> zext(high_shift);
}
@endif
@ifndef IS_ISA
:evsrwu S,A,B is OP=4 & S & A & B & XOP_0_10=544
{
vectorShiftRightWordUnsigned(S,A,B);
local low:4 = A[0,32];
local high:4 = A[32,32];
local low_shift:1 = B[0,5];
local high_shift:1 = B[32,5];
S[0,32] = low >> zext(low_shift);
S[32,32] = high >> zext(high_shift);
}
@endif
@endif
:evstdd RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=801
{
@ -73,32 +89,20 @@ define pcodeop vectorShiftRightWordUnsigned;
RT = RA;
}
@if REGISTER_SIZE=="8"
# evmergehilo rD,rA,rB 010 0010 1110
define pcodeop VectorMergeHighLow;
:evmergehilo D,A,B is OP=4 & A & B & D & XOP_0_10=558 {
local lo = (A & 0x00000000FFFFFFFF);
local hi = ((A & 0xFFFFFFFF00000000) >> 32);
#local b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);
local b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);
:evmergehilo S,A,B is OP=4 & S & A & B & XOP_0_10=558 {
S[32,32] = A[32,32];
S[ 0,32] = B[ 0,32];
lo = lo;
hi = b_hi;
D = ((hi << 32) | lo);
}
# evmergelohi rD,rA,rB 010 0010 1111
:evmergelohi D,A,B is OP=4 & D & A & B & XOP_0_10=559 {
local lo = (A & 0x00000000FFFFFFFF);
local hi = ((A & 0xFFFFFFFF00000000) >> 32);
local b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);
#local b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);
lo = lo;
hi = b_lo;
D = ((hi << 32) | lo);
:evmergelohi S,A,B is OP=4 & S & A & B & XOP_0_10=559 {
S[32,32] = A[ 0,32];
S[ 0,32] = B[32,32];
}
@endif
# evstwwe rS,rA,UIMM 011 0011 1001
:evstwwe RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=0x339