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Merge remote-tracking branch 'origin/Ghidra_11.2'

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ghidra1 2024-09-18 16:16:30 -04:00
commit 17c93909bb
1 changed files with 18 additions and 10 deletions
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Ghidra/Processors/MIPS/data/languages/MIPS.opinion
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@ -102,7 +102,6 @@ Elf e_flags are used for the secondary attribute, the following are pulled from
<constraint primary="8,10" processor="MIPS" size="32" variant="default" compilerSpecID="eabi"
secondary= "0b 01.1 ..00 .... .... 0011 0.0. 0000 ...."/>
<!-- MIPS32-R1 and -R2, with microMIPS, don't cares: MDMX, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="micro"
secondary= "0b 0111 .010 .... .... 00.1 0.0. 0000 ...."/>
@ -112,6 +111,15 @@ Elf e_flags are used for the secondary attribute, the following are pulled from
secondary= "0b 0111 .010 .... .... 0011 0.0. 0000 ...."/>
<!-- MIPS64 Pre-Release 6 -->
<!-- MIPS III,IV with 32-bit addresses, ABI2 don't cares: MDMX, MIPS16e, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" compilerSpecID="n32"
secondary= "0b 001. ..00 .... .... 0... 0.0. 0010 ...."/>
<!-- MIPS III,IV with 32-bit addresses, ABI2 don't cares: MDMX, MIPS16e, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr-micro" compilerSpecID="n32"
secondary= "0b 001. .010 .... .... 0... 0.0. 0010 ...."/>
<!-- MIPS64-R1 with 32-bit addresses, don't cares: MDMX, MIPS16e, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr"
secondary= "0b 0110 ..00 .... .... 0... 0.0. 00.0 ...."/>