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Merge remote-tracking branch 'origin/GP-3733_ghidracadabra_PR-5208_jobermayr_fxsave'
This commit is contained in:
Ryan Kurtz
commit
08a25714de
@ -4436,240 +4436,45 @@ define pcodeop fsin;
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:FXCH freg is vexMode=0 & byte=0xD9; frow=12 & fpage=1 & freg { local tmp = ST0; ST0 = freg; freg = tmp; }
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:FXCH is vexMode=0 & byte=0xD9; byte=0xC9 { local tmp = ST0; ST0 = ST1; ST1 = tmp; }
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# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
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# fxsave and fxrstor
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define pcodeop _fxsave;
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define pcodeop _fxrstor;
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@ifdef IA64
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define pcodeop _fxsave64;
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define pcodeop _fxrstor64;
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@endif
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# this saves the FPU state into 512 bytes of memory
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:FXSAVE Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
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{
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# not saved in the same spacing as the actual processor
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*:2 (Mem) = FPUControlWord;
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*:2 (Mem + 2) = FPUStatusWord;
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*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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*:2 (Mem + 6) = FPULastInstructionOpcode;
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*:4 (Mem + 8) = FPUInstructionPointer;
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*:2 (Mem + 12) = FPUPointerSelector;
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*:4 (Mem + 16) = FPUDataPointer;
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*:2 (Mem + 20) = FPUDataSelector;
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*:4 (Mem + 24) = MXCSR;
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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_fxsave(Mem);
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}
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# saved the FPU ST registers to the ST/MM area of the structure,
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*:10 (Mem + 32) = ST0;
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*:10 (Mem + 48) = ST1;
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*:10 (Mem + 64) = ST2;
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*:10 (Mem + 80) = ST3;
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*:10 (Mem + 96) = ST4;
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*:10 (Mem + 112) = ST5;
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*:10 (Mem + 128) = ST6;
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*:10 (Mem + 144) = ST7;
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*:16 (Mem + 160) = XMM0;
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*:16 (Mem + 176) = XMM1;
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*:16 (Mem + 192) = XMM2;
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*:16 (Mem + 208) = XMM3;
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*:16 (Mem + 224) = XMM4;
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*:16 (Mem + 240) = XMM5;
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*:16 (Mem + 256) = XMM6;
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*:16 (Mem + 272) = XMM7;
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:FXRSTOR Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
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{
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_fxrstor(Mem);
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}
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@ifdef IA64
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# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
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:FXSAVE Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
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{
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*:2 (Mem) = FPUControlWord;
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*:2 (Mem + 2) = FPUStatusWord;
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*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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*:2 (Mem + 6) = FPULastInstructionOpcode;
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*:4 (Mem + 8) = FPUInstructionPointer;
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*:2 (Mem + 12) = FPUPointerSelector;
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*:4 (Mem + 16) = FPUDataPointer;
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*:2 (Mem + 20) = FPUDataSelector;
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*:4 (Mem + 24) = MXCSR;
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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# saved the FPU ST registers to the ST/MM area of the structure,
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*:10 (Mem + 32) = ST0;
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*:10 (Mem + 48) = ST1;
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*:10 (Mem + 64) = ST2;
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*:10 (Mem + 80) = ST3;
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*:10 (Mem + 96) = ST4;
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*:10 (Mem + 112) = ST5;
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*:10 (Mem + 128) = ST6;
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*:10 (Mem + 144) = ST7;
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*:16 (Mem + 160) = XMM0;
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*:16 (Mem + 176) = XMM1;
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*:16 (Mem + 192) = XMM2;
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*:16 (Mem + 208) = XMM3;
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*:16 (Mem + 224) = XMM4;
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*:16 (Mem + 240) = XMM5;
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*:16 (Mem + 256) = XMM6;
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*:16 (Mem + 272) = XMM7;
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*:16 (Mem + 288) = XMM8;
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*:16 (Mem + 304) = XMM9;
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*:16 (Mem + 320) = XMM10;
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*:16 (Mem + 336) = XMM11;
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*:16 (Mem + 352) = XMM12;
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*:16 (Mem + 368) = XMM13;
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*:16 (Mem + 384) = XMM14;
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*:16 (Mem + 400) = XMM15;
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_fxsave(Mem);
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}
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# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
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:FXSAVE64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
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{
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*:2 (Mem) = FPUControlWord;
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*:2 (Mem + 2) = FPUStatusWord;
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*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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*:2 (Mem + 6) = FPULastInstructionOpcode;
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*:8 (Mem + 8) = FPUInstructionPointer;
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*:8 (Mem + 16) = FPUDataPointer;
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*:4 (Mem + 24) = MXCSR;
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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# saved the FPU ST registers to the ST/MM area of the structure,
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*:10 (Mem + 32) = ST0;
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*:10 (Mem + 48) = ST1;
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*:10 (Mem + 64) = ST2;
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*:10 (Mem + 80) = ST3;
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*:10 (Mem + 96) = ST4;
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*:10 (Mem + 112) = ST5;
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*:10 (Mem + 128) = ST6;
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*:10 (Mem + 144) = ST7;
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*:16 (Mem + 160) = XMM0;
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*:16 (Mem + 176) = XMM1;
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*:16 (Mem + 192) = XMM2;
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*:16 (Mem + 208) = XMM3;
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*:16 (Mem + 224) = XMM4;
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*:16 (Mem + 240) = XMM5;
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*:16 (Mem + 256) = XMM6;
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*:16 (Mem + 272) = XMM7;
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*:16 (Mem + 288) = XMM8;
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*:16 (Mem + 304) = XMM9;
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*:16 (Mem + 320) = XMM10;
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*:16 (Mem + 336) = XMM11;
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*:16 (Mem + 352) = XMM12;
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*:16 (Mem + 368) = XMM13;
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*:16 (Mem + 384) = XMM14;
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*:16 (Mem + 400) = XMM15;
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}
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@endif
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:FXRSTOR Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
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{
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FPUControlWord = *:2 (Mem);
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FPUStatusWord = *:2 (Mem + 2);
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FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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FPULastInstructionOpcode = *:2 (Mem + 6);
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FPUInstructionPointer = *:4 (Mem + 8);
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FPUPointerSelector = *:2 (Mem + 12);
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FPUDataPointer = *:4 (Mem + 16);
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FPUDataSelector = *:2 (Mem + 20);
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MXCSR = *:4 (Mem + 24);
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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# saved the FPU ST registers to the ST/MM area of the structure,
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ST0 = *:10 (Mem + 32);
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ST1 = *:10 (Mem + 48);
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ST2 = *:10 (Mem + 64);
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ST3 = *:10 (Mem + 80);
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ST4 = *:10 (Mem + 96);
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ST5 = *:10 (Mem + 112);
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ST6 = *:10 (Mem + 128);
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ST7 = *:10 (Mem + 144);
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XMM0 = *:16 (Mem + 160);
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XMM1 = *:16 (Mem + 176);
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XMM2 = *:16 (Mem + 192);
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XMM3 = *:16 (Mem + 208);
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XMM4 = *:16 (Mem + 224);
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XMM5 = *:16 (Mem + 240);
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XMM6 = *:16 (Mem + 256);
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XMM7 = *:16 (Mem + 272);
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}
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@ifdef IA64
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:FXRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
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{
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FPUControlWord = *:2 (Mem);
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FPUStatusWord = *:2 (Mem + 2);
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FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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FPULastInstructionOpcode = *:2 (Mem + 6);
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FPUInstructionPointer = *:8 (Mem + 8);
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FPUDataPointer = *:8 (Mem + 16);
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MXCSR = *:4 (Mem + 24);
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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# saved the FPU ST registers to the ST/MM area of the structure,
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ST0 = *:10 (Mem + 32);
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ST1 = *:10 (Mem + 48);
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ST2 = *:10 (Mem + 64);
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ST3 = *:10 (Mem + 80);
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ST4 = *:10 (Mem + 96);
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ST5 = *:10 (Mem + 112);
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ST6 = *:10 (Mem + 128);
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ST7 = *:10 (Mem + 144);
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XMM0 = *:16 (Mem + 160);
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XMM1 = *:16 (Mem + 176);
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XMM2 = *:16 (Mem + 192);
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XMM3 = *:16 (Mem + 208);
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XMM4 = *:16 (Mem + 224);
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XMM5 = *:16 (Mem + 240);
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XMM6 = *:16 (Mem + 256);
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XMM7 = *:16 (Mem + 272);
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XMM8 = *:16 (Mem + 288);
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XMM9 = *:16 (Mem + 304);
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XMM10 = *:16 (Mem + 320);
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XMM11 = *:16 (Mem + 336);
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XMM12 = *:16 (Mem + 352);
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XMM13 = *:16 (Mem + 368);
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XMM14 = *:16 (Mem + 384);
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XMM15 = *:16 (Mem + 400);
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_fxsave64(Mem);
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}
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:FXRSTOR Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
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{
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FPUControlWord = *:2 (Mem);
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FPUStatusWord = *:2 (Mem + 2);
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FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
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FPULastInstructionOpcode = *:2 (Mem + 6);
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FPUInstructionPointer = *:4 (Mem + 8);
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FPUPointerSelector = *:2 (Mem + 12);
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FPUDataPointer = *:4 (Mem + 16);
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FPUDataSelector = *:2 (Mem + 20);
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MXCSR = *:4 (Mem + 24);
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# MXCSR_MASK not modeled, since it is processor specific, set to 0.
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_fxrstor(Mem);
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}
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# saved the FPU ST registers to the ST/MM area of the structure,
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ST0 = *:10 (Mem + 32);
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ST1 = *:10 (Mem + 48);
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ST2 = *:10 (Mem + 64);
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ST3 = *:10 (Mem + 80);
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ST4 = *:10 (Mem + 96);
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ST5 = *:10 (Mem + 112);
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ST6 = *:10 (Mem + 128);
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ST7 = *:10 (Mem + 144);
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XMM0 = *:16 (Mem + 160);
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XMM1 = *:16 (Mem + 176);
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XMM2 = *:16 (Mem + 192);
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XMM3 = *:16 (Mem + 208);
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XMM4 = *:16 (Mem + 224);
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XMM5 = *:16 (Mem + 240);
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XMM6 = *:16 (Mem + 256);
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XMM7 = *:16 (Mem + 272);
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XMM8 = *:16 (Mem + 288);
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XMM9 = *:16 (Mem + 304);
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XMM10 = *:16 (Mem + 320);
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XMM11 = *:16 (Mem + 336);
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XMM12 = *:16 (Mem + 352);
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XMM13 = *:16 (Mem + 368);
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XMM14 = *:16 (Mem + 384);
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XMM15 = *:16 (Mem + 400);
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:FXRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
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{
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_fxrstor64(Mem);
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}
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@endif
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