Minki/rvc
1
0
Fork 0
mirror of https://github.com/PiMaker/rvc.git synced 2024-11-10 06:00:07 +00:00
Code Issues Packages Projects Releases Wiki Activity
A 32 bit RISC-V emulator made using a shader
2 Commits 1 Branch 0 Tags 76 MiB
Makefile 55.2%
HTML 13.3%
C 10.3%
Python 9.1%
Shell 5.2%
Other 6.4%
cf50244181
Go to file
Stefan cf50244181 support for all necessary CSRs, privilege modes, traps, atomics 
...plus some cleanups and debug improvements (single-step mode)

All tests specified in test.sh now pass! This pretty much means full
compliance with the RV32I base spec, M and A extensions, as well as correct
machine, supervisor and user mode traps/switches.

Next up is the SV32 MMU and external devices (UART, CLINT timer).
2021-05-28 19:02:11 +02:00
elfy initial commit 2021-05-28 15:10:51 +02:00
riscv-opcodes@7d1a0e3153 initial commit 2021-05-28 15:10:51 +02:00
riscv-rust@b4895fc56b support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
riscv-tests@09cfdaacd9 initial commit 2021-05-28 15:10:51 +02:00
src support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
.gitignore initial commit 2021-05-28 15:10:51 +02:00
.gitmodules support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
instructions.txt initial commit 2021-05-28 15:10:51 +02:00
Makefile initial commit 2021-05-28 15:10:51 +02:00
parse_ins.pl initial commit 2021-05-28 15:10:51 +02:00
test.sh support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00