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A 32 bit RISC-V emulator made using a shader
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Stefan cb6d05178b add MMU support (SV32) and fix a bunch of bugs
2021-08-17 09:31:46 +02:00
elfy implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
linux@25423f4bd9 add MMU support (SV32) and fix a bunch of bugs 2021-08-17 09:31:46 +02:00
opensbi@f30b18944e implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
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riscv-rust@b4895fc56b support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
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README.md

rvc - risc v in c

An experimental 32-bit [0] RISC-V emulator written in plain C [1], with a focus on porting the result to a HLSL pixel shader.

Mostly based on takahirox/riscv-rust, which is a great resource for learning about RISC-V in general, aside from the official specs of course.

[0] GPUs only really support 32-bit integer math (in the use-case I want to put this in anyway)
[1] The elf loader ('elfy') is written in Rust, because I was too lazy to do it myself in C (Rust uses the 'elf' crate) and it doesn't need porting anyway.

Why?

Because.

License

MIT. Take it or leave it.