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A 32 bit RISC-V emulator made using a shader
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Stefan 7f47c7655d Add rust_payload and fixes to allow running it as supervisor 
Note that the 'riscv32ima-unknown-none-elf' target is not available by
default in rustc, you need a patched version.

I'm also pretty sure just converting the ELF binary to raw using objdump
messes with stack and heap addresses, but it seems to work fine for now.
2021-06-09 18:38:46 +02:00
elfy implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
opensbi@f30b18944e implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
riscv-opcodes@7d1a0e3153 initial commit 2021-05-28 15:10:51 +02:00
riscv-rust@b4895fc56b support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
riscv-tests@1b2c3ea84a implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
rust_payload Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00
src Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00
.gitignore Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00
.gitmodules implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
dts.dts Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00
dts.dts.final implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
instructions.txt initial commit 2021-05-28 15:10:51 +02:00
LICENSE Create LICENSE 2021-05-28 17:10:08 +00:00
Makefile Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00
parse_ins.pl initial commit 2021-05-28 15:10:51 +02:00
README.md Update README.md 2021-05-28 17:14:10 +00:00
test.sh Add rust_payload and fixes to allow running it as supervisor 2021-06-09 18:38:46 +02:00

README.md

rvc - risc v in c

An experimental 32-bit [0] RISC-V emulator written in plain C [1], with a focus on porting the result to a HLSL pixel shader.

Mostly based on takahirox/riscv-rust, which is a great resource for learning about RISC-V in general, aside from the official specs of course.

[0] GPUs only really support 32-bit integer math (in the use-case I want to put this in anyway)
[1] The elf loader ('elfy') is written in Rust, because I was too lazy to do it myself in C (Rust uses the 'elf' crate) and it doesn't need porting anyway.

Why?

Because.

License

MIT. Take it or leave it.