A 32 bit RISC-V emulator made using a shader
Go to file
2021-08-17 09:50:08 +02:00
bare_metal_test add bare-metal test image and update .gitignore 2021-08-17 09:37:49 +02:00
buildroot-2021.05 add slightly modified buildroot 2021-08-17 09:44:17 +02:00
elfy implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
linux@25423f4bd9 add MMU support (SV32) and fix a bunch of bugs 2021-08-17 09:31:46 +02:00
mprv add micropython with riscv32 port 2021-08-17 09:49:37 +02:00
opensbi@7aa6c9aa96 update opensbi version and add optional performance patch 2021-08-17 09:43:14 +02:00
riscv-opcodes@7d1a0e3153 initial commit 2021-05-28 15:10:51 +02:00
riscv-rust@b4895fc56b support for all necessary CSRs, privilege modes, traps, atomics 2021-05-28 19:02:11 +02:00
riscv-tests@1b2c3ea84a implement UART, CLINT, device tree, opensbi build 2021-06-03 22:45:13 +02:00
rust_payload update rust_payload 2021-08-17 09:50:08 +02:00
src fix riscv-tests and add flag for exit call 2021-08-17 09:36:49 +02:00
toimg add 'toimg' rust source, converts data to Unity textures 2021-08-17 09:45:29 +02:00
.gitignore add 'toimg' rust source, converts data to Unity textures 2021-08-17 09:45:29 +02:00
.gitmodules add micropython with riscv32 port 2021-08-17 09:49:37 +02:00
dts.dts update device tree 2021-08-17 09:42:13 +02:00
instructions.txt initial commit 2021-05-28 15:10:51 +02:00
LICENSE Create LICENSE 2021-05-28 17:10:08 +00:00
linux-_pi_-patches-for-rvc.patch add linux kernel, custom patches and update Makefile 2021-08-17 09:41:21 +02:00
linux.config add linux kernel, custom patches and update Makefile 2021-08-17 09:41:21 +02:00
Makefile add linux kernel, custom patches and update Makefile 2021-08-17 09:41:21 +02:00
opensbi-don-t-zero-BSS.patch update opensbi version and add optional performance patch 2021-08-17 09:43:14 +02:00
parse_ins.pl initial commit 2021-05-28 15:10:51 +02:00
README.md Update README.md 2021-05-28 17:14:10 +00:00
test.sh fix riscv-tests and add flag for exit call 2021-08-17 09:36:49 +02:00

rvc - risc v in c

An experimental 32-bit [0] RISC-V emulator written in plain C [1], with a focus on porting the result to a HLSL pixel shader.

Mostly based on takahirox/riscv-rust, which is a great resource for learning about RISC-V in general, aside from the official specs of course.

[0] GPUs only really support 32-bit integer math (in the use-case I want to put this in anyway)
[1] The elf loader ('elfy') is written in Rust, because I was too lazy to do it myself in C (Rust uses the 'elf' crate) and it doesn't need porting anyway.

Why?

Because.

License

MIT. Take it or leave it.