/dts-v1/; / { #address-cells = <0x2>; #size-cells = <0x2>; compatible = "riscv-virtio"; model = "generic,rvc"; aliases { serial0 = &uart0; }; chosen { bootargs = "root=mtd:root rootfstype=romfs ro init=/rvcinit phram.phram=root,0x40000000,256Mi console=hvc0 earlycon=sbi"; stdout-path = "/uart@10000000"; }; uart0: uart@10000000 { /* interrupts = <0x9>; */ /* interrupt-parent = <&irqchip>; */ clock-frequency = <0x384000>; reg = <0x0 0x10000000 0x0 0x100>; compatible = "ns16550a"; }; rtc@3000000 { compatible = "maxim,ds1742"; reg = <0x0 0x3000000 0x0 0x800>; }; rvcnet { compatible = "pi,rvcnet"; }; cpus { #address-cells = <0x1>; #size-cells = <0x0>; /* 100/20 kHz, must match frequency in emu.h */ timebase-frequency = <0x1388>; cpu-map { cluster0 { core0 { cpu = <0x1>; }; }; }; cpu@0 { device_type = "cpu"; reg = <0x0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv32imasu"; mmu-type = "riscv,sv32"; irqchip: interrupt-controller { #address-cells = <0x1>; #interrupt-cells = <0x1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x07B00000>; /* includes safety margin at end? */ }; soc { #address-cells = <0x2>; #size-cells = <0x2>; compatible = "simple-bus"; ranges; clint@2000000 { interrupts-extended = <&irqchip 0x3 &irqchip 0x7>; reg = <0x0 0x2000000 0x0 0x10000>; compatible = "riscv,clint0"; }; }; };