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add bare-metal test image and update .gitignore
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parent
30bd88dbbf
commit
9c936f211c
4
.gitignore
vendored
4
.gitignore
vendored
@ -9,3 +9,7 @@ rust_payload/target
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rust_payload/Cargo.lock
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fw_payload.*
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*.dtb
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*.bmp
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*.bin
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*.elf
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*.img
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34
bare_metal_test/Makefile
Normal file
34
bare_metal_test/Makefile
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@ -0,0 +1,34 @@
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TARGET ?= bare
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SRC_DIRS ?= .
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PREFIX ?= ../buildroot-2021.05/output/host/bin/riscv32-buildroot-linux-gnu-
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CC := $(PREFIX)cc
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AS := $(PREFIX)as
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LD := $(PREFIX)ld
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OBJDUMP := $(PREFIX)objcopy
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SRCS := $(wildcard *.S)
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SRCS += $(wildcard *.c)
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OBJS := $(addsuffix .o,$(basename $(SRCS)))
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DEPS := $(OBJS:.o=.d)
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INC_DIRS := $(shell find $(SRC_DIRS) -type d)
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INC_FLAGS := $(addprefix -I,$(INC_DIRS))
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CFLAGS += -O3 -march=rv32ima -mabi=ilp32 -fno-stack-protector -fno-pie
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ASFLAGS += -march=rv32ima -mabi=ilp32
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LDFLAGS += -static -nostdlib -nostartfiles -nodefaultlibs -Triscv32.ld -Wl,--no-as-needed
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$(TARGET): $(OBJS)
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$(CC) $(LDFLAGS) $(OBJS) -o $@ $(LOADLIBES) $(LDLIBS)
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$(TARGET).img: $(TARGET)
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riscv32-elf-objcopy -O binary $< $@
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.PHONY: clean
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clean:
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$(RM) $(TARGET) $(OBJS) $(DEPS)
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.PHONY: run
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run: $(TARGET).img
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../rvc -d ../dts.dtb -b $(TARGET).img
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BIN
bare_metal_test/bare
Executable file
BIN
bare_metal_test/bare
Executable file
Binary file not shown.
52
bare_metal_test/bare.c
Normal file
52
bare_metal_test/bare.c
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@ -0,0 +1,52 @@
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#include <stdbool.h>
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#define UART_THR (*(volatile unsigned char*)0x10000000)
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#define UART_LSR (*(volatile unsigned char*)0x10000005)
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#define UART_LSR_THRE 0x20
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// wait for Transfer Hold Register to clear, then write character to print it
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void uart_putc(unsigned char c) {
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while (UART_THR || !(UART_LSR & UART_LSR_THRE)) {}
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UART_THR = c;
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}
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void print(const char* str) {
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while (*str) {
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uart_putc(*str++);
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}
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}
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static bool got_ssip = false;
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volatile static long long a = 0xaaaaffffffff;
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// runs in supervisor mode via mideleg (machine-mode trap delegation)
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void handle_trap(void) {
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print("[bare/trap] got SSIP!\n");
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got_ssip = true;
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}
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// called from assembly, runs in supervisor mode (via sret)
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int main(void) {
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print("[bare] in main()\n");
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print("[bare] testing arithmetic...\n");
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long long b = a * 400LLU * -1;
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if (b != -0x10AAB2FFFFFFE70LL) {
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print("[bare] got wrong result :(\n");
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} else {
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print("[bare] got correct result!\n");
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}
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print("[bare] testing trap handler...\n");
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__asm volatile("csrw sip, 0x2");
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while (!got_ssip) {}
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print("[bare] selftest done!\n");
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print("[bare] now go run something more exciting...\n");
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while (true) {}
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return 0;
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}
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137
bare_metal_test/init.S
Normal file
137
bare_metal_test/init.S
Normal file
@ -0,0 +1,137 @@
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#define SLL32 sll
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#define STORE sw
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#define LOAD lw
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#define LWU lw
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#define LOG_REGBYTES 2
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#define REGBYTES (1 << LOG_REGBYTES)
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.section .entry, "ax", %progbits
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.align 4
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.globl _start
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_start:
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csrw mie, zero
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csrw mip, zero
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lla a3, _start_hang
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csrw mtvec, a3
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lla a3, _s_trap_entry
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csrw stvec, a3
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# enable supervisor software interrupt
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li a3, 0x2
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csrw sie, a3
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csrw mie, a3
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csrw mideleg, a3
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li a3, 0x00b
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csrs mstatus, a3
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lla sp, _estack
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lla a3, main
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csrw mepc, a3
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li a3, 0x800
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csrs mstatus, a3
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mret
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j _start_hang
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.section .entry, "ax", %progbits
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.align 4
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.globl _start_hang
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_start_hang:
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j _start_hang
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.section .entry, "ax", %progbits
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.align 4
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.globl _trap_entry
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_s_trap_entry:
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addi sp,sp,-320
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# save gprs
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STORE x1,1*REGBYTES(x2)
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STORE x3,3*REGBYTES(x2)
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STORE x4,4*REGBYTES(x2)
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STORE x5,5*REGBYTES(x2)
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STORE x6,6*REGBYTES(x2)
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STORE x7,7*REGBYTES(x2)
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STORE x8,8*REGBYTES(x2)
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STORE x9,9*REGBYTES(x2)
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STORE x10,10*REGBYTES(x2)
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STORE x11,11*REGBYTES(x2)
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STORE x12,12*REGBYTES(x2)
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STORE x13,13*REGBYTES(x2)
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STORE x14,14*REGBYTES(x2)
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STORE x15,15*REGBYTES(x2)
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STORE x16,16*REGBYTES(x2)
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STORE x17,17*REGBYTES(x2)
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STORE x18,18*REGBYTES(x2)
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STORE x19,19*REGBYTES(x2)
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STORE x20,20*REGBYTES(x2)
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STORE x21,21*REGBYTES(x2)
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STORE x22,22*REGBYTES(x2)
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STORE x23,23*REGBYTES(x2)
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STORE x24,24*REGBYTES(x2)
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STORE x25,25*REGBYTES(x2)
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STORE x26,26*REGBYTES(x2)
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STORE x27,27*REGBYTES(x2)
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STORE x28,28*REGBYTES(x2)
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STORE x29,29*REGBYTES(x2)
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STORE x30,30*REGBYTES(x2)
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STORE x31,31*REGBYTES(x2)
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# get sr, epc, badvaddr, cause
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csrr s0, sstatus
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csrr t1, sepc
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csrr t2, stval
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csrr t3, scause
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STORE t0, 2*REGBYTES(x2)
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STORE s0, 32*REGBYTES(x2)
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STORE t1, 33*REGBYTES(x2)
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STORE t2, 34*REGBYTES(x2)
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STORE t3, 35*REGBYTES(x2)
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move a0, sp
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jal handle_trap
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mv a0, sp
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addi sp, sp, 320
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LOAD t0, 32*REGBYTES(a0)
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LOAD t1, 33*REGBYTES(a0)
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csrw sstatus, t0
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csrw sepc, t1
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# restore x registers
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LOAD x1,1*REGBYTES(a0)
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LOAD x2,2*REGBYTES(a0)
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LOAD x3,3*REGBYTES(a0)
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LOAD x4,4*REGBYTES(a0)
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LOAD x5,5*REGBYTES(a0)
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LOAD x6,6*REGBYTES(a0)
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LOAD x7,7*REGBYTES(a0)
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LOAD x8,8*REGBYTES(a0)
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LOAD x9,9*REGBYTES(a0)
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LOAD x11,11*REGBYTES(a0)
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LOAD x12,12*REGBYTES(a0)
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LOAD x13,13*REGBYTES(a0)
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LOAD x14,14*REGBYTES(a0)
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LOAD x15,15*REGBYTES(a0)
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LOAD x16,16*REGBYTES(a0)
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LOAD x17,17*REGBYTES(a0)
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LOAD x18,18*REGBYTES(a0)
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LOAD x19,19*REGBYTES(a0)
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LOAD x20,20*REGBYTES(a0)
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LOAD x21,21*REGBYTES(a0)
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LOAD x22,22*REGBYTES(a0)
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LOAD x23,23*REGBYTES(a0)
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LOAD x24,24*REGBYTES(a0)
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LOAD x25,25*REGBYTES(a0)
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LOAD x26,26*REGBYTES(a0)
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LOAD x27,27*REGBYTES(a0)
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LOAD x28,28*REGBYTES(a0)
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LOAD x29,29*REGBYTES(a0)
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LOAD x30,30*REGBYTES(a0)
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LOAD x31,31*REGBYTES(a0)
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# restore a0 last
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LOAD x10,10*REGBYTES(a0)
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# gtfo
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sret
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34
bare_metal_test/riscv32.ld
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34
bare_metal_test/riscv32.ld
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MEMORY
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{
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RAM : ORIGIN = 0x80000000, LENGTH = 31M
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}
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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SECTIONS
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{
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.text :
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{
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. = ALIGN(4);
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*(.entry)
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*(.text)
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*(.text*)
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*(.rodata)
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*(.rodata*)
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} >RAM
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.data :
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{
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. = ALIGN(4);
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*(.data)
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*(.data*)
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} >RAM
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.bss :
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{
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. = ALIGN(4);
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*(.bss)
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*(.bss*)
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*(COMMON)
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} >RAM
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}
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