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update device tree

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This commit is contained in:
Stefan 2021-08-17 09:42:13 +02:00
parent 81e95a6791
commit 17da3478bd
2 changed files with 10 additions and 91 deletions
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20
dts.dts
View File

@ -7,13 +7,13 @@
model = "generic,rvc";
chosen {
bootargs = "ttyS0";
stdout-path = "/uart@10000000";
bootargs = "console=hvc0 earlycon=sbi loglevel=15 debug single";
//stdout-path = "/uart@10000000";
};
uart@10000000 {
interrupts = <0x1>;
interrupt-parent = <0x2>;
interrupt-parent = <&irqchip>;
clock-frequency = <0x384000>;
reg = <0x0 0x10000000 0x0 0x100>;
compatible = "ns16550a";
@ -22,7 +22,7 @@
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
timebase-frequency = <0x989680>;
timebase-frequency = <0x1000000>;
cpu-map {
cluster0 {
@ -33,15 +33,15 @@
};
cpu@0 {
phandle = <0x1>;
device_type = "cpu";
reg = <0x0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imasu";
riscv,isa = "rv32imasu";
mmu-type = "riscv,sv32";
interrupt-controller {
phandle = <0x2>;
irqchip: interrupt-controller {
#address-cells = <0x1>;
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
@ -51,7 +51,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x8000000>;
reg = <0x0 0x80000000 0x0 0x03B00000>; /* includes safety margin at end? */
};
soc {
@ -61,7 +61,7 @@
ranges;
clint@2000000 {
interrupts-extended = <0x2 0x3 0x2 0x7>;
interrupts-extended = <&irqchip 0x3 &irqchip 0x7>;
reg = <0x0 0x2000000 0x0 0x10000>;
compatible = "riscv,clint0";
};

81
dts.dts.final
View File

@ -1,81 +0,0 @@
/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "riscv-virtio";
model = "riscv-virtio,qemu";
chosen {
bootargs = "ttyS0";
stdout-path = "/uart@10000000";
};
uart@10000000 {
interrupts = <0x1>;
interrupt-parent = <0x3>;
clock-frequency = <0x384000>;
reg = <0x0 0x10000000 0x0 0x100>;
compatible = "ns16550a";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
timebase-frequency = <0x989680>;
cpu-map {
cluster0 {
core0 {
cpu = <0x1>;
};
};
};
cpu@0 {
phandle = <0x1>;
device_type = "cpu";
reg = <0x0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imasu";
mmu-type = "riscv,sv32";
interrupt-controller {
phandle = <0x2>;
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x8000000>;
};
soc {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "simple-bus";
ranges;
interrupt-controller@c000000 {
phandle = <0x3>;
riscv,ndev = <0x35>;
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <0x2 0xb 0x2 0x9>;
interrupt-controller;
compatible = "riscv,plic0";
#interrupt-cells = <0x1>;
#address-cells = <0x0>;
};
clint@2000000 {
interrupts-extended = <0x2 0x3 0x2 0x7>;
reg = <0x0 0x2000000 0x0 0x10000>;
compatible = "riscv,clint0";
};
};
};