mirror of
https://github.com/torvalds/linux.git
synced 2024-11-14 16:12:02 +00:00
af866496c7
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2942/ Patchwork: https://patchwork.linux-mips.org/patch/3012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
102 lines
2.9 KiB
Plaintext
102 lines
2.9 KiB
Plaintext
if CPU_CAVIUM_OCTEON
|
|
|
|
config CAVIUM_CN63XXP1
|
|
bool "Enable CN63XXP1 errata worarounds"
|
|
default "n"
|
|
help
|
|
The CN63XXP1 chip requires build time workarounds to
|
|
function reliably, select this option to enable them. These
|
|
workarounds will cause a slight decrease in performance on
|
|
non-CN63XXP1 hardware, so it is recommended to select "n"
|
|
unless it is known the workarounds are needed.
|
|
|
|
config CAVIUM_OCTEON_2ND_KERNEL
|
|
bool "Build the kernel to be used as a 2nd kernel on the same chip"
|
|
default "n"
|
|
help
|
|
This option configures this kernel to be linked at a different
|
|
address and use the 2nd uart for output. This allows a kernel built
|
|
with this option to be run at the same time as one built without this
|
|
option.
|
|
|
|
config CAVIUM_OCTEON_HW_FIX_UNALIGNED
|
|
bool "Enable hardware fixups of unaligned loads and stores"
|
|
default "y"
|
|
help
|
|
Configure the Octeon hardware to automatically fix unaligned loads
|
|
and stores. Normally unaligned accesses are fixed using a kernel
|
|
exception handler. This option enables the hardware automatic fixups,
|
|
which requires only an extra 3 cycles. Disable this option if you
|
|
are running code that relies on address exceptions on unaligned
|
|
accesses.
|
|
|
|
config CAVIUM_OCTEON_CVMSEG_SIZE
|
|
int "Number of L1 cache lines reserved for CVMSEG memory"
|
|
range 0 54
|
|
default 1
|
|
help
|
|
CVMSEG LM is a segment that accesses portions of the dcache as a
|
|
local memory; the larger CVMSEG is, the smaller the cache is.
|
|
This selects the size of CVMSEG LM, which is in cache blocks. The
|
|
legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
|
|
between zero and 6192 bytes).
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2
|
|
bool "Lock often used kernel code in the L2"
|
|
default "y"
|
|
help
|
|
Enable locking parts of the kernel into the L2 cache.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_TLB
|
|
bool "Lock the TLB handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level TLB fast path into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
|
|
bool "Lock the exception handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level exception handler into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
|
|
bool "Lock the interrupt handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level interrupt handler into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
|
|
bool "Lock the 2nd level interrupt handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the 2nd level interrupt handler in L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_MEMCPY
|
|
bool "Lock memcpy() in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the kernel's implementation of memcpy() into L2.
|
|
|
|
config ARCH_SPARSEMEM_ENABLE
|
|
def_bool y
|
|
select SPARSEMEM_STATIC
|
|
|
|
config IOMMU_HELPER
|
|
bool
|
|
|
|
config NEED_SG_DMA_LENGTH
|
|
bool
|
|
|
|
config SWIOTLB
|
|
def_bool y
|
|
select IOMMU_HELPER
|
|
select NEED_SG_DMA_LENGTH
|
|
|
|
|
|
endif # CPU_CAVIUM_OCTEON
|