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On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual address for a cacheable mapping of a location is being accessed by a core while another core is remapping the virtual address to a new physical page using the recommended break-before-make sequence, then under very rare circumstances TLBI+DSB completes before a read using the translation being invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation and is shared with the Qualcomm Falkor erratum 1009 Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
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| .. | ||
| acpi_object_usage.txt | ||
| arm-acpi.txt | ||
| booting.txt | ||
| cpu-feature-registers.txt | ||
| elf_hwcaps.txt | ||
| hugetlbpage.txt | ||
| legacy_instructions.txt | ||
| memory.txt | ||
| silicon-errata.txt | ||
| sve.txt | ||
| tagged-pointers.txt | ||