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The VersaClock driver now supports some additional bindings to support child nodes which can configure optional settings like mode, voltage and slew. This patch updates the binding document to describe what is available in the driver. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200603154329.31579-2-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
14 lines
280 B
C
14 lines
280 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* This file defines field values used by the versaclock 6 family
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* for defining output type
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*/
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#define VC5_LVPECL 0
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#define VC5_CMOS 1
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#define VC5_HCSL33 2
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#define VC5_LVDS 3
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#define VC5_CMOS2 4
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#define VC5_CMOSD 5
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#define VC5_HCSL25 6
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