mirror of
https://github.com/torvalds/linux.git
synced 2024-09-29 11:23:16 +00:00
adf7589997
A while back we added {read,write}_sysreg accessors to handle accesses
to system registers, without the usual boilerplate asm volatile,
temporary variable, etc.
This patch makes use of these across arm64 to make code shorter and
clearer. For sequences with a trailing ISB, the existing isb() macro is
also used so that asm blocks can be removed entirely.
A few uses of inline assembly for msr/mrs are left as-is. Those
manipulating sp_el0 for the current thread_info value have special
clobber requiremends.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/*
|
|
* ARM64 cacheinfo support
|
|
*
|
|
* Copyright (C) 2015 ARM Ltd.
|
|
* All Rights Reserved
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
* kind, whether express or implied; without even the implied warranty
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include <linux/bitops.h>
|
|
#include <linux/cacheinfo.h>
|
|
#include <linux/cpu.h>
|
|
#include <linux/compiler.h>
|
|
#include <linux/of.h>
|
|
|
|
#include <asm/cachetype.h>
|
|
#include <asm/processor.h>
|
|
|
|
#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
|
|
/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
|
|
#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
|
|
#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
|
|
#define CLIDR_CTYPE(clidr, level) \
|
|
(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
|
|
|
|
static inline enum cache_type get_cache_type(int level)
|
|
{
|
|
u64 clidr;
|
|
|
|
if (level > MAX_CACHE_LEVEL)
|
|
return CACHE_TYPE_NOCACHE;
|
|
clidr = read_sysreg(clidr_el1);
|
|
return CLIDR_CTYPE(clidr, level);
|
|
}
|
|
|
|
/*
|
|
* Cache Size Selection Register(CSSELR) selects which Cache Size ID
|
|
* Register(CCSIDR) is accessible by specifying the required cache
|
|
* level and the cache type. We need to ensure that no one else changes
|
|
* CSSELR by calling this in non-preemtible context
|
|
*/
|
|
u64 __attribute_const__ cache_get_ccsidr(u64 csselr)
|
|
{
|
|
u64 ccsidr;
|
|
|
|
WARN_ON(preemptible());
|
|
|
|
write_sysreg(csselr, csselr_el1);
|
|
isb();
|
|
ccsidr = read_sysreg(ccsidr_el1);
|
|
|
|
return ccsidr;
|
|
}
|
|
|
|
static void ci_leaf_init(struct cacheinfo *this_leaf,
|
|
enum cache_type type, unsigned int level)
|
|
{
|
|
bool is_icache = type & CACHE_TYPE_INST;
|
|
u64 tmp = cache_get_ccsidr((level - 1) << 1 | is_icache);
|
|
|
|
this_leaf->level = level;
|
|
this_leaf->type = type;
|
|
this_leaf->coherency_line_size = CACHE_LINESIZE(tmp);
|
|
this_leaf->number_of_sets = CACHE_NUMSETS(tmp);
|
|
this_leaf->ways_of_associativity = CACHE_ASSOCIATIVITY(tmp);
|
|
this_leaf->size = this_leaf->number_of_sets *
|
|
this_leaf->coherency_line_size * this_leaf->ways_of_associativity;
|
|
this_leaf->attributes =
|
|
((tmp & CCSIDR_EL1_WRITE_THROUGH) ? CACHE_WRITE_THROUGH : 0) |
|
|
((tmp & CCSIDR_EL1_WRITE_BACK) ? CACHE_WRITE_BACK : 0) |
|
|
((tmp & CCSIDR_EL1_READ_ALLOCATE) ? CACHE_READ_ALLOCATE : 0) |
|
|
((tmp & CCSIDR_EL1_WRITE_ALLOCATE) ? CACHE_WRITE_ALLOCATE : 0);
|
|
}
|
|
|
|
static int __init_cache_level(unsigned int cpu)
|
|
{
|
|
unsigned int ctype, level, leaves;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
|
|
for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
|
|
ctype = get_cache_type(level);
|
|
if (ctype == CACHE_TYPE_NOCACHE) {
|
|
level--;
|
|
break;
|
|
}
|
|
/* Separate instruction and data caches */
|
|
leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
|
|
}
|
|
|
|
this_cpu_ci->num_levels = level;
|
|
this_cpu_ci->num_leaves = leaves;
|
|
return 0;
|
|
}
|
|
|
|
static int __populate_cache_leaves(unsigned int cpu)
|
|
{
|
|
unsigned int level, idx;
|
|
enum cache_type type;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
|
|
|
|
for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
|
|
idx < this_cpu_ci->num_leaves; idx++, level++) {
|
|
type = get_cache_type(level);
|
|
if (type == CACHE_TYPE_SEPARATE) {
|
|
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
|
|
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
|
|
} else {
|
|
ci_leaf_init(this_leaf++, type, level);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
|