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SCDC is the Status and Control Data Channel for HDMI. Move the SCDC helpers into display/ and split the header into files for core and helpers. Update all affected drivers. No functional changes. To avoid the proliferation of Kconfig options, SCDC is part of DRM's support for HDMI. If necessary, a new option could make SCDC an independent feature. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-9-tzimmermann@suse.de
89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
/*
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* Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef DRM_SCDC_H
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#define DRM_SCDC_H
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#define SCDC_SINK_VERSION 0x01
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#define SCDC_SOURCE_VERSION 0x02
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#define SCDC_UPDATE_0 0x10
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#define SCDC_READ_REQUEST_TEST (1 << 2)
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#define SCDC_CED_UPDATE (1 << 1)
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#define SCDC_STATUS_UPDATE (1 << 0)
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#define SCDC_UPDATE_1 0x11
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#define SCDC_TMDS_CONFIG 0x20
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#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
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#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
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#define SCDC_SCRAMBLING_ENABLE (1 << 0)
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#define SCDC_SCRAMBLER_STATUS 0x21
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#define SCDC_SCRAMBLING_STATUS (1 << 0)
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#define SCDC_CONFIG_0 0x30
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#define SCDC_READ_REQUEST_ENABLE (1 << 0)
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#define SCDC_STATUS_FLAGS_0 0x40
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#define SCDC_CH2_LOCK (1 << 3)
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#define SCDC_CH1_LOCK (1 << 2)
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#define SCDC_CH0_LOCK (1 << 1)
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#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
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#define SCDC_CLOCK_DETECT (1 << 0)
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#define SCDC_STATUS_FLAGS_1 0x41
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#define SCDC_ERR_DET_0_L 0x50
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#define SCDC_ERR_DET_0_H 0x51
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#define SCDC_ERR_DET_1_L 0x52
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#define SCDC_ERR_DET_1_H 0x53
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#define SCDC_ERR_DET_2_L 0x54
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#define SCDC_ERR_DET_2_H 0x55
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#define SCDC_CHANNEL_VALID (1 << 7)
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#define SCDC_ERR_DET_CHECKSUM 0x56
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#define SCDC_TEST_CONFIG_0 0xc0
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#define SCDC_TEST_READ_REQUEST (1 << 7)
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#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
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#define SCDC_MANUFACTURER_IEEE_OUI 0xd0
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#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
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#define SCDC_DEVICE_ID 0xd3
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#define SCDC_DEVICE_ID_SIZE 8
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#define SCDC_DEVICE_HARDWARE_REVISION 0xdb
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#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
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#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
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#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
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#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
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#define SCDC_MANUFACTURER_SPECIFIC 0xde
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#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
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#endif
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