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* Support for various vector-accelerated crypto routines. * Hibernation is now enabled for portable kernel builds. * mmap_rnd_bits_max is larger on systems with larger VAs. * Support for fast GUP. * Support for membarrier-based instruction cache synchronization. * Support for the Andes hart-level interrupt controller and PMU. * Some cleanups around unaligned access speed probing and Kconfig settings. * Support for ACPI LPI and CPPC. * Various cleanus related to barriers. * A handful of fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmX9icgTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYib+UD/4xyL6UMixx6A06BVBL9UT4vOrxRvNr JIihG5y5QNMjes9DHWL35mZTMqFtQ0tq94ViWFLmJWloV/8KRVM2C9R9KX7vplf3 M/OwvP106spxgvNHoeQbycgs42RU1t2mpqT7N1iK2hCjqieP3vLn6hsSLXWTAG0L 3gQbQw6XCLC3hPyLq+nbFY2i4faeCmpXWmixoy/IvQ5calZQrRU0LNlP6lcMBhVo uocjG0uGAhrahw2s81jxcMZcxa3AvUCiplapdD5H5v9rBM85SkYJj2Q9SqdSorkb xzuimRnKPI5s47yM3pTfZY0qnQUYHV7PXXuw4WujpCQVQdhaG+Ggq63UUZA61J9t IzZK2zdcfHqICrGTtXImUzRT3dcc3oq+IFq4tTY+rEJm29hrXkAtx+qBm5xtMvax fJz5feJ/iT0u7MDj4Oq24n+Kpl+Olm+MJaZX3m5Ovi/9V6a9iK9HXqxg9/Fs0fMO +J/0kTgd8Vu9CYH7KNWz3uztcO9eMAH3VyzuXuab4BGj1i1Y/9EjpALQi7rDN73S OsYQX6NnzMkBV4dvElJVLXiPlvNlMHZZwdak5CqPb48jaJu6iiIZAuvOrG6/naGP wnQSLVA2WWWoOkl3AJhxfpa11CLhbMl9E2gYm1VtNvASXoSFIxlAq1Yv3sG8yjty 4ZT0rYFJOstYiQ== =3dL5 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ... |
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arch | ||
Build | ||
empty-pmu-events.c | ||
jevents.py | ||
metric_test.py | ||
metric.py | ||
pmu-events.h | ||
README |
The contents of this directory allow users to specify PMU events in their CPUs by their symbolic names rather than raw event codes (see example below). The main program in this directory, is the 'jevents', which is built and executed _BEFORE_ the perf binary itself is built. The 'jevents' program tries to locate and process JSON files in the directory tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - The CSV file that maps a specific CPU to its set of PMU events is to be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored. - To reduce JSON event duplication per architecture, platform JSONs may use "ArchStdEvent" keyword to dereference an "Architecture standard events", defined in architecture standard JSONs. Architecture standard JSONs must be located in the architecture root folder. Matching is based on the "EventName" field. The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies the topic. Eg: "Floating-point.json". All the topic JSON files for a CPU model/family should be in a separate sub directory. Thus for the Silvermont X86 CPU: $ ls tools/perf/pmu-events/arch/x86/silvermont cache.json memory.json virtual-memory.json frontend.json pipeline.json The JSONs folder for a CPU model/family may be placed in the root arch folder, or may be placed in a vendor sub-folder under the arch folder for instances where the arch and vendor are not the same. Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: - Set of 'PMU events tables' for all known CPUs in the architecture, (one table like the following, per JSON file; table name 'pme_power8' is derived from JSON file name, 'power8.json'). struct pmu_event pme_power8[] = { ... { .name = "pm_1plus_ppc_cmpl", .event = "event=0x100f2", .desc = "1 or more ppc insts finished,", }, ... } - A 'mapping table' that maps each CPU of the architecture, to its 'PMU events table' struct pmu_events_map pmu_events_map[] = { { .cpuid = "004b0000", .version = "1", .type = "core", .table = pme_power8 }, ... }; After the 'pmu-events.c' is generated, it is compiled and the resulting 'pmu-events.o' is added to 'libperf.a' which is then used to build perf. NOTES: 1. Several CPUs can support same set of events and hence use a common JSON file. Hence several entries in the pmu_events_map[] could map to a single 'PMU events table'. 2. The 'pmu-events.h' has an extern declaration for the mapping table and the generated 'pmu-events.c' defines this table. 3. _All_ known CPU tables for architecture are included in the perf binary. At run time, perf determines the actual CPU it is running on, finds the matching events table and builds aliases for those events. This allows users to specify events by their name: $ perf stat -e pm_1plus_ppc_cmpl sleep 1 where 'pm_1plus_ppc_cmpl' is a Power8 PMU event. However some errors in processing may cause the alias build to fail. Mapfile format =============== The mapfile enables multiple CPU models to share a single set of PMU events. It is required even if such mapping is 1:1. The mapfile.csv format is expected to be: Header line CPUID,Version,Dir/path/name,Type where: Comma: is the required field delimiter (i.e other fields cannot have commas within them). Comments: Lines in which the first character is either '\n' or '#' are ignored. Header line The header line is the first line in the file, which is always _IGNORED_. It can be empty. CPUID: CPUID is an arch-specific char string, that can be used to identify CPU (and associate it with a set of PMU events it supports). Multiple CPUIDS can point to the same File/path/name.json. Example: CPUID == 'GenuineIntel-6-2E' (on x86). CPUID == '004b0100' (PVR value in Powerpc) Version: is the Version of the mapfile. Dir/path/name: is the pathname to the directory containing the CPU's JSON files, relative to the directory containing the mapfile.csv Type: indicates whether the events are "core" or "uncore" events. Eg: $ grep silvermont tools/perf/pmu-events/arch/x86/mapfile.csv GenuineIntel-6-37,v13,silvermont,core GenuineIntel-6-4D,v13,silvermont,core GenuineIntel-6-4C,v13,silvermont,core i.e the three CPU models use the JSON files (i.e PMU events) listed in the directory 'tools/perf/pmu-events/arch/x86/silvermont'.