linux/drivers/clk/hisilicon
Stephen Boyd 74ca928886 Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx' into clk-next
* clk-hisi:
  clk: hi6220: use CLK_OF_DECLARE_DRIVER

* clk-amlogic:
  clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
  clk: meson: axg_audio: add sm1 support
  clk: meson: axg-audio: provide clk top signal name
  clk: meson: axg-audio: prepare sm1 addition
  clk: meson: axg-audio: fix regmap last register
  clk: meson: axg-audio: remove useless defines
  dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  dt-bindings: clk: axg-audio: add sm1 bindings
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

* clk-samsung:
  clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
  clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
  clk: samsung: exynos5420: Add VPLL rate table
  clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
  clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
  clk: samsung: exynos5433: Fix error paths

* clk-renesas: (23 commits)
  clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
  clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
  dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
  clk: renesas: r8a77965: Remove superfluous semicolon
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
  dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
  clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
  clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
  clk: renesas: r8a774b1: Add TMU clock
  clk: renesas: cpg-mssr: Add r8a774b1 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
  clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
  clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
  clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
  clk: renesas: rcar-gen3: Improve arithmetic divisions
  clk: renesas: rcar-gen2: Improve arithmetic divisions
  clk: renesas: Remove R-Car Gen2 legacy DT clock support
  ...

* clk-imx:
  clk: imx: imx8mq: fix sys3_pll_out_sels
  clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
  clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx7ulp: Correct DDR clock mux options
  clk: imx7ulp: Correct system clock source option #7
  clk: imx: imx8mq: mark sys1/2_pll as fixed clock
  clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
  clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
  clk: imx8mn: Define gates for pll1/2 fixed dividers
  clk: imx8mm: Define gates for pll1/2 fixed dividers
  clk: imx8mq: Define gates for pll1/2 fixed dividers
  clk: imx: clk-pll14xx: Make two variables static
  clk: imx8mq: Add VIDEO2_PLL clock
  clk: imx8mn: Use common 1443X/1416X PLL clock structure
  clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
  clk: imx: pll14xx: Fix quick switch of S/K parameter
2019-11-27 08:14:17 -08:00
..
clk-hi3519.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk-hi3620.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 2019-05-21 11:28:39 +02:00
clk-hi3660-stub.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-hi3660.c clk: hisilicon: fix sparse warnings in clk-hi3660.c 2019-10-03 13:31:33 -07:00
clk-hi3670.c clk: hisilicon: fix sparse warnings in clk-hi3670.c 2019-10-03 13:31:33 -07:00
clk-hi6220-stub.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clk-hi6220.c clk: hi6220: use CLK_OF_DECLARE_DRIVER 2019-10-28 08:07:52 -07:00
clk-hip04.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 2019-05-21 11:28:39 +02:00
clk-hisi-phase.c clk: core: replace clk_{readl,writel} with {readl,writel} 2019-04-23 10:57:49 -07:00
clk-hix5hd2.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422 2019-06-05 17:37:15 +02:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 2019-05-21 11:28:39 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 2019-05-21 11:28:39 +02:00
clkdivider-hi6220.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clkgate-separated.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 2019-05-21 11:28:39 +02:00
crg-hi3516cv300.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
crg-hi3798cv200.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
crg.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
Kconfig treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
Makefile clk: hisilicon: Add clock driver for Hi3670 SoC 2018-10-16 14:47:16 -07:00
reset.c clk: hisilicon: use devm_platform_ioremap_resource() to simplify code 2019-10-16 16:17:06 -07:00
reset.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00