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35a17eb6a8
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
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* irq.h: IRQ registers on the 64-bit Sparc.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#ifndef _SPARC64_IRQ_H
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#define _SPARC64_IRQ_H
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/pil.h>
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#include <asm/ptrace.h>
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/* IMAP/ICLR register defines */
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#define IMAP_VALID 0x80000000 /* IRQ Enabled */
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#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
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#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
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#define IMAP_TID_SHIFT 26
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#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
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#define IMAP_AID_SHIFT 26
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#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
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#define IMAP_NID_SHIFT 21
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#define IMAP_IGN 0x000007c0 /* IRQ Group Number */
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#define IMAP_INO 0x0000003f /* IRQ Number */
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#define IMAP_INR 0x000007ff /* Full interrupt number*/
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#define ICLR_IDLE 0x00000000 /* Idle state */
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#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
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#define ICLR_PENDING 0x00000003 /* Pending state */
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/* The largest number of unique interrupt sources we support.
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* If this needs to ever be larger than 255, you need to change
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* the type of ino_bucket->virt_irq as appropriate.
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*
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* ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
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*/
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#define NR_IRQS 255
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extern void irq_install_pre_handler(int virt_irq,
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void (*func)(unsigned int, void *, void *),
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void *arg1, void *arg2);
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#define irq_canonicalize(irq) (irq)
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extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
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extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
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extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
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unsigned int msi_devino_start,
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unsigned int msi_devino_end);
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extern void sun4v_destroy_msi(unsigned int virt_irq);
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extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
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static __inline__ void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ void clear_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ unsigned long get_softint(void)
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{
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unsigned long retval;
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__asm__ __volatile__("rd %%softint, %0"
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: "=r" (retval));
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return retval;
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}
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#endif
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