linux/arch/ia64/kernel
akpm@osdl.org 198e2f1811 [PATCH] scheduler cache-hot-autodetect
)

From: Ingo Molnar <mingo@elte.hu>

This is the latest version of the scheduler cache-hot-auto-tune patch.

The first problem was that detection time scaled with O(N^2), which is
unacceptable on larger SMP and NUMA systems. To solve this:

- I've added a 'domain distance' function, which is used to cache
  measurement results. Each distance is only measured once. This means
  that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT
  distances 0 and 1, and on SMP distance 0 is measured. The code walks
  the domain tree to determine the distance, so it automatically follows
  whatever hierarchy an architecture sets up. This cuts down on the boot
  time significantly and removes the O(N^2) limit. The only assumption
  is that migration costs can be expressed as a function of domain
  distance - this covers the overwhelming majority of existing systems,
  and is a good guess even for more assymetric systems.

  [ People hacking systems that have assymetries that break this
    assumption (e.g. different CPU speeds) should experiment a bit with
    the cpu_distance() function. Adding a ->migration_distance factor to
    the domain structure would be one possible solution - but lets first
    see the problem systems, if they exist at all. Lets not overdesign. ]

Another problem was that only a single cache-size was used for measuring
the cost of migration, and most architectures didnt set that variable
up. Furthermore, a single cache-size does not fit NUMA hierarchies with
L3 caches and does not fit HT setups, where different CPUs will often
have different 'effective cache sizes'. To solve this problem:

- Instead of relying on a single cache-size provided by the platform and
  sticking to it, the code now auto-detects the 'effective migration
  cost' between two measured CPUs, via iterating through a wide range of
  cachesizes. The code searches for the maximum migration cost, which
  occurs when the working set of the test-workload falls just below the
  'effective cache size'. I.e. real-life optimized search is done for
  the maximum migration cost, between two real CPUs.

  This, amongst other things, has the positive effect hat if e.g. two
  CPUs share a L2/L3 cache, a different (and accurate) migration cost
  will be found than between two CPUs on the same system that dont share
  any caches.

(The reliable measurement of migration costs is tricky - see the source
for details.)

Furthermore i've added various boot-time options to override/tune
migration behavior.

Firstly, there's a blanket override for autodetection:

	migration_cost=1000,2000,3000

will override the depth 0/1/2 values with 1msec/2msec/3msec values.

Secondly, there's a global factor that can be used to increase (or
decrease) the autodetected values:

	migration_factor=120

will increase the autodetected values by 20%. This option is useful to
tune things in a workload-dependent way - e.g. if a workload is
cache-insensitive then CPU utilization can be maximized by specifying
migration_factor=0.

I've tested the autodetection code quite extensively on x86, on 3
P3/Xeon/2MB, and the autodetected values look pretty good:

Dual Celeron (128K L2 cache):

 ---------------------
 migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):
 ---------------------
           [00]    [01]
 [00]:     -     1.7(1)
 [01]:   1.7(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (0) 1.7 (1784008)
 ---------------------

Here the slow memory subsystem dominates system performance, and even
though caches are small, the migration cost is 1.7 msecs.

Dual HT P4 (512K L2 cache):

 ---------------------
 migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):
 ---------------------
           [00]    [01]    [02]    [03]
 [00]:     -     0.4(1)  0.0(0)  0.4(1)
 [01]:   0.4(1)    -     0.4(1)  0.0(0)
 [02]:   0.0(0)  0.4(1)    -     0.4(1)
 [03]:   0.4(1)  0.0(0)  0.4(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (33900) 0.4 (448514)
 ---------------------

Here it can be seen that there is no migration cost between two HT
siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory
system makes inter-physical-CPU migration pretty cheap: 0.4 msecs.

8-way P3/Xeon [2MB L2 cache]:

 ---------------------
 migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):
 ---------------------
           [00]    [01]    [02]    [03]    [04]    [05]    [06]    [07]
 [00]:     -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [01]:  19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [02]:  19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [03]:  19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [04]:  19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1)
 [05]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1)
 [06]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1)
 [07]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (0) 19.2 (19281756)
 ---------------------

This one has huge caches and a relatively slow memory subsystem - so the
migration cost is 19 msecs.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Cc: <wilder@us.ibm.com>
Signed-off-by: John Hawkes <hawkes@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:50 -08:00
..
cpufreq [IA64] Add ACPI based P-state support 2005-08-26 15:09:24 -07:00
acpi-ext.c [ACPI] Lindent all ACPI files 2005-08-05 00:45:14 -04:00
acpi.c [IA64] move ACPI IOSAPIC locality domain mapping from pci.c to acpi.c 2005-09-19 15:57:48 -07:00
asm-offsets.c [IA64] fix circular dependency on generation of asm-offsets.h 2005-09-13 08:50:39 -07:00
brl_emu.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
cyclone.c [PATCH] fix missing includes 2005-10-30 17:37:32 -08:00
efi_stub.S Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
efi.c [PATCH] /dev/mem: validate mmap requests 2006-01-08 20:14:02 -08:00
entry.h [IA64] Drop spurious paren in entry.h 2005-06-20 09:34:02 -07:00
entry.S [PATCH] Swap Migration V5: sys_migrate_pages interface 2006-01-08 20:12:42 -08:00
fsys.S kbuild: ia64 use generic asm-offsets.h support 2005-09-09 22:03:13 +02:00
gate-data.S Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
gate.lds.S Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
gate.S kbuild: ia64 use generic asm-offsets.h support 2005-09-09 22:03:13 +02:00
head.S [PATCH] remove gcc-2 checks 2006-01-08 20:14:02 -08:00
ia64_ksyms.c [PATCH] remove gcc-2 checks 2006-01-08 20:14:02 -08:00
init_task.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
iosapic.c [IA64] Manual merge fix for 3 files 2005-09-08 14:27:13 -07:00
irq_ia64.c [IA64] assign_irq_vector() should not panic 2005-07-11 10:30:07 -07:00
irq_lsapic.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
irq.c [IA64] wider use of for_each_cpu_mask() in arch/ia64 2005-10-25 15:10:08 -07:00
ivt.S [IA64] polish comments for tlb fault handler in ivt.S 2005-11-17 09:48:15 -08:00
jprobes.S [PATCH] Kprobes: prevent possible race conditions ia64 changes 2005-09-07 16:58:00 -07:00
kprobes.c [PATCH] kprobes: fix race in recovery of reentrant probe 2006-01-11 18:42:12 -08:00
machvec.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
Makefile [PATCH] cpusets: Move the ia64 domain setup code to the generic code 2005-09-07 16:57:40 -07:00
mca_asm.S [IA64] Wire in the MCA/INIT handler stacks 2005-09-22 13:24:19 -07:00
mca_drv_asm.S [IA64] mca_drv cleanup 2005-09-16 10:39:40 -07:00
mca_drv.c Pull mca-check-psp into release branch 2005-11-10 10:38:05 -08:00
mca_drv.h [IA64] mca_drv cleanup 2005-09-16 10:39:40 -07:00
mca.c [IA64] Extend notify_die() hooks for IA64 2005-11-07 11:27:13 -08:00
minstate.h [IA64] MCA/INIT: remove the physical mode path from minstate.h 2005-09-11 14:09:12 -07:00
module.c [IA64] wider use of for_each_cpu_mask() in arch/ia64 2005-10-25 15:10:08 -07:00
numa.c [IA64] fix generic/up builds 2005-07-06 18:18:10 -07:00
pal.S Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
palinfo.c [IA64] Allow /proc/pal/cpu0/vm_info under the simulator 2005-08-31 08:34:51 -07:00
patch.c [IA64] Fix 2.6 kernel for the new ia64 assembler 2005-10-25 15:05:45 -07:00
perfmon_default_smpl.c [IA64] perfmon: make pfm_sysctl a global, and other cleanup 2005-04-25 13:08:30 -07:00
perfmon_generic.h Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
perfmon_itanium.h Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
perfmon_mckinley.h Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
perfmon.c [PATCH] capable/capability.h (arch/) 2006-01-11 18:42:14 -08:00
process.c [IA64] fix for SET_PERSONALITY when CONFIG_IA32_SUPPORT is not set. 2005-12-14 08:52:57 -08:00
ptrace.c [PATCH] use ptrace_get_task_struct in various places 2006-01-08 20:13:51 -08:00
sal.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
salinfo.c [PATCH] capable/capability.h (arch/) 2006-01-11 18:42:14 -08:00
semaphore.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
setup.c [PATCH] scheduler cache-hot-autodetect 2006-01-12 09:08:50 -08:00
sigframe.h Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
signal.c [IA64] align signal-frame even when not using alternate signal-stack 2005-11-08 09:58:06 -08:00
smp.c [IA64] wider use of for_each_cpu_mask() in arch/ia64 2005-10-25 15:10:08 -07:00
smpboot.c [PATCH] sched: disable preempt in idle tasks 2005-11-09 07:56:33 -08:00
sys_ia64.c [IA64] Rationalise Region Definitions 2005-08-24 15:35:41 -07:00
time.c [IA64] disable preemption in udelay() 2005-12-16 10:00:24 -08:00
topology.c [ACPI] delete CONFIG_ACPI_BOOT 2005-08-24 12:08:54 -04:00
traps.c [IA64] Remove getting break_num by decoding instruction 2005-11-29 09:24:39 -08:00
unaligned.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
uncached.c [IA64] uncached ref count leak 2005-12-16 10:29:52 -08:00
unwind_decoder.c Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
unwind_i.h Linux-2.6.12-rc2 2005-04-16 15:20:36 -07:00
unwind.c [IA64] MCA/INIT: remove obsolete unwind code 2005-09-11 14:09:34 -07:00
vmlinux.lds.S [IA64] Add __read_mostly support for IA64 2005-12-16 10:52:46 -08:00