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4de067e5df
For EDIF + N2N to work, firmware 9.8 or later is required. The driver will pause after PLOGI to allow app to authenticate. Once authentication completes, app will tell driver to do PRLI. Link: https://lore.kernel.org/r/20210817051315.2477-6-njavali@marvell.com Signed-off-by: Quinn Tran <qutran@marvell.com> Signed-off-by: Nilesh Javali <njavali@marvell.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Marvell Fibre Channel HBA Driver
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* Copyright (c) 2021 Marvell
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*/
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#ifndef __QLA_EDIF_H
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#define __QLA_EDIF_H
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struct qla_scsi_host;
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#define EDIF_APP_ID 0x73730001
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#define EDIF_MAX_INDEX 2048
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struct edif_sa_ctl {
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struct list_head next;
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uint16_t del_index;
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uint16_t index;
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uint16_t slot;
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uint16_t flags;
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#define EDIF_SA_CTL_FLG_REPL BIT_0
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#define EDIF_SA_CTL_FLG_DEL BIT_1
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#define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
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// Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
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unsigned long state;
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#define EDIF_SA_CTL_USED 1 /* Active Sa update */
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#define EDIF_SA_CTL_PEND 2 /* Waiting for slot */
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#define EDIF_SA_CTL_REPL 3 /* Active Replace and Delete */
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#define EDIF_SA_CTL_DEL 4 /* Delete Pending */
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struct fc_port *fcport;
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struct bsg_job *bsg_job;
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struct qla_sa_update_frame sa_frame;
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};
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enum enode_flags_t {
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ENODE_ACTIVE = 0x1,
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};
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struct pur_core {
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enum enode_flags_t enode_flags;
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spinlock_t pur_lock;
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struct list_head head;
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};
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enum db_flags_t {
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EDB_ACTIVE = 0x1,
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};
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struct edif_dbell {
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enum db_flags_t db_flags;
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spinlock_t db_lock;
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struct list_head head;
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struct completion dbell;
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};
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#define SA_UPDATE_IOCB_TYPE 0x71 /* Security Association Update IOCB entry */
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struct sa_update_28xx {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System Defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* IOCB System handle. */
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union {
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__le16 nport_handle; /* in: N_PORT handle. */
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__le16 comp_sts; /* out: completion status */
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#define CS_PORT_EDIF_UNAVAIL 0x28
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#define CS_PORT_EDIF_LOGOUT 0x29
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#define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
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#define CS_PORT_EDIF_INV_REQ 0x66
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} u;
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uint8_t vp_index;
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uint8_t reserved_1;
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uint8_t port_id[3];
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uint8_t flags;
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#define SA_FLAG_INVALIDATE BIT_0
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#define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
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uint8_t sa_key[32]; /* 256 bit key */
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__le32 salt;
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__le32 spi;
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uint8_t sa_control;
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#define SA_CNTL_ENC_FCSP (1 << 3)
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#define SA_CNTL_ENC_OPD (2 << 3)
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#define SA_CNTL_ENC_MSK (3 << 3) // mask bits 4,3
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#define SA_CNTL_AES_GMAC (1 << 2)
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#define SA_CNTL_KEY256 (2 << 0)
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#define SA_CNTL_KEY128 0
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uint8_t reserved_2;
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__le16 sa_index; // reserve: bit 11-15
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__le16 old_sa_info;
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__le16 new_sa_info;
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};
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#define NUM_ENTRIES 256
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#define MAX_PAYLOAD 1024
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#define PUR_GET 1
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struct dinfo {
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int nodecnt;
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int lstate;
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};
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struct pur_ninfo {
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unsigned int pur_pend:1;
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port_id_t pur_sid;
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port_id_t pur_did;
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uint8_t vp_idx;
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short pur_bytes_rcvd;
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unsigned short pur_nphdl;
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unsigned int pur_rx_xchg_address;
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};
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struct purexevent {
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struct pur_ninfo pur_info;
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unsigned char *msgp;
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u32 msgp_len;
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};
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#define N_UNDEF 0
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#define N_PUREX 1
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struct enode {
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struct list_head list;
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struct dinfo dinfo;
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uint32_t ntype;
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union {
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struct purexevent purexinfo;
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} u;
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};
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#define EDIF_SESSION_DOWN(_s) \
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(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
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_s->disc_state == DSC_DELETED || \
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!_s->edif.app_sess_online))
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#endif /* __QLA_EDIF_H */
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