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Register an 'nvdimm-bridge' device to act as an anchor for a libnvdimm bus hierarchy. Also, flesh out the cxl_bus definition to allow a cxl_nvdimm_bridge_driver to attach to the bridge and trigger the nvdimm-bus registration. The creation of the bridge is gated on the detection of a PMEM capable address space registered to the root. The bridge indirection allows the libnvdimm module to remain unloaded on platforms without PMEM support. Given that the probing of ACPI0017 is asynchronous to CXL endpoint devices, and the expectation that CXL endpoint devices register other PMEM resources on the 'CXL' nvdimm bus, a workqueue is added. The workqueue is needed to run bus_rescan_devices() outside of the device_lock() of the nvdimm-bridge device to rendezvous nvdimm resources as they arrive. For now only the bus is taken online/offline in the workqueue. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162379909706.2993820.14051258608641140169.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
79 lines
3.0 KiB
Plaintext
79 lines
3.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig CXL_BUS
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tristate "CXL (Compute Express Link) Devices Support"
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depends on PCI
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help
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CXL is a bus that is electrically compatible with PCI Express, but
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layers three protocols on that signalling (CXL.io, CXL.cache, and
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CXL.mem). The CXL.cache protocol allows devices to hold cachelines
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locally, the CXL.mem protocol allows devices to be fully coherent
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memory targets, the CXL.io protocol is equivalent to PCI Express.
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Say 'y' to enable support for the configuration and management of
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devices supporting these protocols.
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if CXL_BUS
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config CXL_MEM
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tristate "CXL.mem: Memory Devices"
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default CXL_BUS
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help
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The CXL.mem protocol allows a device to act as a provider of
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"System RAM" and/or "Persistent Memory" that is fully coherent
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as if the memory was attached to the typical CPU memory
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controller.
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Say 'y/m' to enable a driver that will attach to CXL.mem devices for
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configuration and management primarily via the mailbox interface. See
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Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
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details.
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If unsure say 'm'.
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config CXL_MEM_RAW_COMMANDS
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bool "RAW Command Interface for Memory Devices"
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depends on CXL_MEM
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help
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Enable CXL RAW command interface.
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The CXL driver ioctl interface may assign a kernel ioctl command
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number for each specification defined opcode. At any given point in
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time the number of opcodes that the specification defines and a device
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may implement may exceed the kernel's set of associated ioctl function
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numbers. The mismatch is either by omission, specification is too new,
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or by design. When prototyping new hardware, or developing / debugging
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the driver it is useful to be able to submit any possible command to
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the hardware, even commands that may crash the kernel due to their
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potential impact to memory currently in use by the kernel.
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If developing CXL hardware or the driver say Y, otherwise say N.
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config CXL_ACPI
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tristate "CXL ACPI: Platform Support"
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depends on ACPI
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default CXL_BUS
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help
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Enable support for host managed device memory (HDM) resources
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published by a platform's ACPI CXL memory layout description. See
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Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
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specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
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(https://www.computeexpresslink.org/spec-landing). The CXL core
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consumes these resource to publish the root of a cxl_port decode
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hierarchy to map regions that represent System RAM, or Persistent
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Memory regions to be managed by LIBNVDIMM.
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If unsure say 'm'.
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config CXL_PMEM
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tristate "CXL PMEM: Persistent Memory Support"
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depends on LIBNVDIMM
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default CXL_BUS
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help
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In addition to typical memory resources a platform may also advertise
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support for persistent memory attached via CXL. This support is
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managed via a bridge driver from CXL to the LIBNVDIMM system
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subsystem. Say 'y/m' to enable support for enumerating and
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provisioning the persistent memory capacity of CXL memory expanders.
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If unsure say 'm'.
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endif
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