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e568006b9d
linux/arch/powerpc/mm
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Aneesh Kumar K.V e568006b9d powerpc/mm/hash: Don't add memory coherence if cache inhibited is set 
H_ENTER hcall handling in qemu had assumptions that a cache inhibited
hpte entry won't have memory conference set. Also older kernel
mentioned that some version of pHyp required this (the code removed
by the below commit says:

    /* Make pHyp happy */
    if ((rflags & _PAGE_NO_CACHE) && !(rflags & _PAGE_WRITETHRU))
            hpte_r &= ~HPTE_R_M;

But with older kernel we had some inconsistent memory conherence
mapping. We always enabled memory conherence in the page fault path and
removed memory conherence is _PAGE_NO_CACHE was set when we mapped the
page via htab_bolt_mapping. The commit mentioned below tried to
consolidate that by always enabling memory conherence. But as mentioned
above that breaks Qemu H_ENTER handling.

This patch update this such that we enable memory conherence only if
cache inhibited is not set and bring fault handling, lpar and bolt
mapping in sync.

Fixes: commit 30bda41aba4e("powerpc/mm: Drop WIMG in favour of new constant")
Reported-by: Darrick J. Wong <darrick.wong@oracle.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-06-17 19:47:51 +10:00
..
8xx_mmu.c powerpc/8xx: rewrite flush_instruction_cache() in C 2016-03-11 17:20:11 -06:00
40x_mmu.c powerpc/mm: Don't use pmd_val, pud_val and pgd_val as lvalue 2015-12-14 15:19:07 +11:00
44x_mmu.c powerpc: Delete __cpuinit usage from all users 2013-07-01 11:10:36 +10:00
copro_fault.c cxl: Move include file cxl.h -> cxl-base.h 2015-06-03 13:27:19 +10:00
dma-noncoherent.c powerpc: Simplify test in __dma_sync() 2016-03-11 17:20:12 -06:00
fault.c powerpc: Add plain English description for alignment exception oopses 2015-07-06 20:24:35 +10:00
fsl_booke_mmu.c powerpc/mm: Convert pte_user() to static inline 2016-05-01 18:32:24 +10:00
hash64_4k.c powerpc/mm/book3s: Rename hash specific PTE bits to carry H_ prefix 2016-05-01 18:32:43 +10:00
hash64_64k.c powerpc/mm/book3s: Rename hash specific PTE bits to carry H_ prefix 2016-05-01 18:32:43 +10:00
hash_low_32.S powerpc: Use CURRENT_THREAD_INFO instead of open coded assembly 2012-07-11 14:18:22 +10:00
hash_native_64.c powerpc/mm/hash: Use the correct PPP mask when updating HPTE 2016-06-14 13:54:51 +10:00
hash_utils_64.c powerpc/mm/hash: Don't add memory coherence if cache inhibited is set 2016-06-17 19:47:51 +10:00
highmem.c sched/preempt, mm/kmap: Explicitly disable/enable preemption in kmap_atomic_* 2015-05-19 08:39:14 +02:00
hugepage-hash64.c powerpc/mm/book3s: Rename hash specific PTE bits to carry H_ prefix 2016-05-01 18:32:43 +10:00
hugetlbpage-book3e.c powerpc/fsl-book3e: Avoid lbarx on e5500 2016-03-03 23:43:05 -06:00
hugetlbpage-hash64.c powerpc/mm/book3s: Rename hash specific PTE bits to carry H_ prefix 2016-05-01 18:32:43 +10:00
hugetlbpage-radix.c powerpc/mm: Add radix support for hugetlb 2016-05-11 21:53:55 +10:00
hugetlbpage.c powerpc updates for 4.7 2016-05-20 10:12:41 -07:00
icswx_pid.c
icswx.c powerpc: Fix typo "CONFIG_ICSWX_PID" 2013-04-18 13:03:54 +10:00
icswx.h
init_32.c powerpc updates for 4.6 2016-03-19 15:38:41 -07:00
init_64.c powerpc/mm: Abstraction for vmemmap and map_kernel_page() 2016-05-01 18:33:02 +10:00
Makefile powerpc/mm/thp: Abstraction for THP functions 2016-05-11 21:53:57 +10:00
mem.c powerpc/mm: Improve readability of update_mmu_cache() 2016-05-11 21:54:09 +10:00
mmap.c powerpc/mm/radix: Pick the address layout for radix config 2016-05-11 21:53:47 +10:00
mmu_context_book3s64.c powerpc/mm/subpage: Initialise user psize correctly 2016-05-11 21:53:59 +10:00
mmu_context_hash32.c powerpc: Remove power3 from comments 2014-07-28 14:10:26 +10:00
mmu_context_iommu.c powerpc/mmu: Add userspace-to-physical addresses translation cache 2015-06-11 15:16:54 +10:00
mmu_context_nohash.c powerpc/mm/slice: Remove slice_mm_new_context() 2016-05-11 21:54:00 +10:00
mmu_decl.h powerpc/mm: Abstraction for vmemmap and map_kernel_page() 2016-05-01 18:33:02 +10:00
numa.c powerpc updates for 4.4 2015-11-05 23:38:43 -08:00
pgtable_32.c powerpc32: PAGE_EXEC required for inittext 2016-03-11 20:04:32 -06:00
pgtable_64.c powerpc/mm: THP is only available on hash64 as of now 2016-05-11 21:53:56 +10:00
pgtable-book3e.c powerpc/mm: Make page table size a variable 2016-05-01 18:32:48 +10:00
pgtable-book3s64.c powerpc/mm/radix: Add missing tlb flush 2016-06-01 13:47:34 +10:00
pgtable-hash64.c powerpc/mm/thp: Abstraction for THP functions 2016-05-11 21:53:57 +10:00
pgtable-radix.c powerpc/mm/radix: Update LPCR only if it is powernv 2016-06-01 13:47:34 +10:00
pgtable.c powerpc/mm: Update pte filter for radix 2016-05-11 21:53:52 +10:00
ppc_mmu_32.c powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together 2016-03-11 17:18:02 -06:00
slb_low.S powerpc/mm: vmalloc abstraction in preparation for radix 2016-05-11 21:53:53 +10:00
slb.c powerpc/mm: Remove long disabled SLB code 2016-04-11 20:30:40 +10:00
slice.c powerpc/mm/radix: Add checks in slice code to catch radix usage 2016-05-11 21:53:46 +10:00
subpage-prot.c thp: rename split_huge_page_pmd() to split_huge_pmd() 2016-01-15 17:56:32 -08:00
tlb_hash32.c
tlb_hash64.c powerpc/mm: Hash abstraction for tlbflush routines 2016-05-01 18:33:08 +10:00
tlb_low_64e.S powerpc: Fix misspellings in comments. 2016-03-01 19:27:20 +11:00
tlb_nohash_low.S powerpc: Fix misspellings in comments. 2016-03-01 19:27:20 +11:00
tlb_nohash.c powerpc/mm: any thread in one core can be the first to setup TLB1 2016-03-04 23:44:02 -06:00
tlb-radix.c powerpc/mm/radix: Flush page walk cache when freeing page table 2016-06-10 16:14:52 +10:00
vphn.c powerpc/vphn: parsing code rewrite 2015-03-18 10:48:59 +11:00
vphn.h powerpc/vphn: parsing code rewrite 2015-03-18 10:48:59 +11:00