Marc Zyngier e48d53a91f arm64: KVM: Add support for Stage-2 control of memory types and cacheability ... Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes results in the strongest attribute of the two stages. This means that the hypervisor has to perform quite a lot of cache maintenance just in case the guest has some non-cacheable mappings around. ARMv8.4 solves this problem by offering a different mode (FWB) where Stage-2 has total control over the memory attribute (this is limited to systems where both I/O and instruction fetches are coherent with the dcache). This is achieved by having a different set of memory attributes in the page tables, and a new bit set in HCR_EL2. On such a system, we can then safely sidestep any form of dcache management. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2018-07-09 11:37:41 +01:00
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kvm	arm64: KVM: Add support for Stage-2 control of memory types and cacheability	2018-07-09 11:37:41 +01:00
lib	KVM: eventfd: fix NULL deref irqbypass consumer	2017-01-12 14:42:34 +01:00
Makefile	virt: Add virt directory to the top Makefile	2015-10-01 15:06:44 +02:00