Swapnil Jakhade e25c9dbcfc phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock ... For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2021-03-30 23:34:13 +05:30
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allwinner	phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg	2020-11-19 11:49:18 +05:30
amlogic	phy: amlogic: replace devm_reset_control_array_get()	2020-11-30 16:32:37 +05:30
broadcom	phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb only	2021-03-15 15:58:24 +05:30
cadence	phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock	2021-03-30 23:34:13 +05:30
freescale	phy: freescale: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
hisilicon	phy: hisilicon; Constify hi3660_phy_ops	2020-08-31 14:36:36 +05:30
ingenic	phy-for-5.12	2021-02-09 09:32:35 +01:00
intel	phy: intel: Fix a typo	2021-03-25 12:54:24 +05:30
lantiq	phy: lantiq: rcu-usb2: wait after clock enable	2021-01-13 19:29:03 +05:30
marvell	drivers: phy: add support for Armada CP110 UTMI PHY	2021-03-30 23:32:53 +05:30
mediatek	phy: second round of phy fixes for v5.11	2021-02-10 10:39:23 +01:00
microchip	phy: Add Sparx5 ethernet serdes PHY driver	2021-03-17 12:13:19 +05:30
motorola	phy-for-5.12	2021-02-09 09:32:35 +01:00
mscc	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
qualcomm	phy: qualcomm: remove duplicate argument	2021-03-25 12:55:40 +05:30
ralink	phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro	2020-12-01 17:14:41 +05:30
renesas	phy: renesas: rcar-gen3-usb2: disable runtime pm in case of failure	2020-12-05 13:36:12 +05:30
rockchip	phy: rockchip-typec: add missing of_node_put	2021-03-15 15:35:32 +05:30
samsung	phy: samsung: Merge Kconfig for Exynos5420 and Exynos5250	2020-12-02 12:35:07 +05:30
socionext	phy: socionext: Add UniPhier AHCI PHY driver support	2020-08-31 17:07:53 +05:30
st	phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock	2021-03-15 15:25:29 +05:30
tegra	phy-for-5.11	2020-12-09 14:26:40 +01:00
ti	phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>	2021-03-30 23:33:38 +05:30
xilinx	phy: zynqmp: Simplify code by using dev_err_probe()	2021-02-06 15:28:15 +05:30
Kconfig	phy: Add Sparx5 ethernet serdes PHY driver	2021-03-17 12:13:19 +05:30
Makefile	phy: Add Sparx5 ethernet serdes PHY driver	2021-03-17 12:13:19 +05:30
phy-core-mipi-dphy.c	phy: dphy: Change units of wakeup and init parameters	2019-02-07 11:11:05 +05:30
phy-core.c	phy: Add media type and speed serdes configuration interfaces	2021-03-17 12:13:19 +05:30
phy-lgm-usb.c	phy: Add USB3 PHY support for Intel LGM SoC	2020-09-11 17:12:49 +05:30
phy-lpc18xx-usb-otg.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
phy-pistachio-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
phy-xgene.c	phy: phy-xgene: convert to devm_platform_ioremap_resource	2020-11-16 12:47:47 +05:30