mirror of
https://github.com/torvalds/linux.git
synced 2024-09-28 02:43:02 +00:00
e24c2d963a
After seeing, at best, "guesses" as to the following kind of information in several drivers, I decided that we really need a way for platforms to specifically give advice in this area for what works best with their PCI controller implementation. Basically, this new interface gives DMA bursting advice on PCI. There are three forms of the advice: 1) Burst as much as possible, it is not necessary to end bursts on some particular boundary for best performance. 2) Burst on some byte count multiple. A DMA burst to some multiple of number of bytes may be done, but it is important to end the burst on an exact multiple for best performance. The best example of this I am aware of are the PPC64 PCI controllers, where if you end a burst mid-cacheline then chip has to refetch the data and the IOMMU translations which hurts performance a lot. 3) Burst on a single byte count multiple. Bursts shall end exactly on the next multiple boundary for best performance. Sparc64 and Alpha's PCI controllers operate this way. They disconnect any device which tries to burst across a cacheline boundary. Actually, newer sparc64 PCI controllers do not have this behavior. That is why the "pdev" is passed into the interface, so I can add code later to check which PCI controller the system is using and give advice accordingly. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
#ifndef ASMARM_PCI_H
|
|
#define ASMARM_PCI_H
|
|
|
|
#ifdef __KERNEL__
|
|
#include <linux/config.h>
|
|
#include <asm-generic/pci-dma-compat.h>
|
|
|
|
#include <asm/hardware.h> /* for PCIBIOS_MIN_* */
|
|
|
|
#define pcibios_scan_all_fns(a, b) 0
|
|
|
|
static inline void pcibios_set_master(struct pci_dev *dev)
|
|
{
|
|
/* No special bus mastering setup handling */
|
|
}
|
|
|
|
static inline void pcibios_penalize_isa_irq(int irq)
|
|
{
|
|
/* We don't do dynamic PCI IRQ allocation */
|
|
}
|
|
|
|
/*
|
|
* The PCI address space does equal the physical memory address space.
|
|
* The networking and block device layers use this boolean for bounce
|
|
* buffer decisions.
|
|
*/
|
|
#define PCI_DMA_BUS_IS_PHYS (0)
|
|
|
|
/*
|
|
* We don't support DAC DMA cycles.
|
|
*/
|
|
#define pci_dac_dma_supported(pci_dev, mask) (0)
|
|
|
|
/*
|
|
* Whether pci_unmap_{single,page} is a nop depends upon the
|
|
* configuration.
|
|
*/
|
|
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME;
|
|
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME;
|
|
#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
|
|
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
|
|
#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
|
|
#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
|
|
|
|
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
|
enum pci_dma_burst_strategy *strat,
|
|
unsigned long *strategy_parameter)
|
|
{
|
|
*strat = PCI_DMA_BURST_INFINITY;
|
|
*strategy_parameter = ~0UL;
|
|
}
|
|
|
|
#define HAVE_PCI_MMAP
|
|
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state, int write_combine);
|
|
|
|
extern void
|
|
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
|
|
struct resource *res);
|
|
|
|
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
|
|
{
|
|
}
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif
|