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e1f1ae8002
The module reset code in the Renesas CPG/MSSR driver uses
read-modify-write (RMW) operations to write to a Software Reset Register
(SRCRn), and simple writes to write to a Software Reset Clearing
Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
User's Manuals.
However, this may cause a race condition when two devices are reset in
parallel: if the reset for device A completes in the middle of the RMW
operation for device B, device A may be reset again, causing subtle
failures (e.g. i2c timeouts):
thread A thread B
-------- --------
val = SRCRn
val |= bit A
SRCRn = val
delay
val = SRCRn (bit A is set)
SRSTCLRn = bit A
(bit A in SRCRn is cleared)
val |= bit B
SRCRn = val (bit A and B are set)
This can be reproduced on e.g. Salvator-XS using:
$ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
$ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &
i2c-rcar e6510000.i2c: error -110 : 40000002
i2c-rcar e66d8000.i2c: error -110 : 40000002
According to the R-Car Gen3 Hardware Manual Errata for Rev.
0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
User's Manual, writes to SRCRn do not require read-modify-write cycles.
Note that the R-Car Gen2 Hardware User's Manual has not been updated
yet, and still says a read-modify-write sequence is required. According
to the hardware team, the reset hardware block is the same on both R-Car
Gen2 and Gen3, though.
Hence fix the issue by replacing the read-modify-write operations on
SRCRn by simple writes.
Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com>
Fixes:
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|---|---|---|
| .. | ||
| clk-div6.c | ||
| clk-div6.h | ||
| clk-emev2.c | ||
| clk-mstp.c | ||
| clk-r8a73a4.c | ||
| clk-r8a7740.c | ||
| clk-r8a7778.c | ||
| clk-r8a7779.c | ||
| clk-rcar-gen2.c | ||
| clk-rz.c | ||
| clk-sh73a0.c | ||
| Kconfig | ||
| Makefile | ||
| r7s9210-cpg-mssr.c | ||
| r8a774a1-cpg-mssr.c | ||
| r8a774c0-cpg-mssr.c | ||
| r8a7743-cpg-mssr.c | ||
| r8a7745-cpg-mssr.c | ||
| r8a7790-cpg-mssr.c | ||
| r8a7791-cpg-mssr.c | ||
| r8a7792-cpg-mssr.c | ||
| r8a7794-cpg-mssr.c | ||
| r8a7795-cpg-mssr.c | ||
| r8a7796-cpg-mssr.c | ||
| r8a77470-cpg-mssr.c | ||
| r8a77965-cpg-mssr.c | ||
| r8a77970-cpg-mssr.c | ||
| r8a77980-cpg-mssr.c | ||
| r8a77990-cpg-mssr.c | ||
| r8a77995-cpg-mssr.c | ||
| r9a06g032-clocks.c | ||
| rcar-gen2-cpg.c | ||
| rcar-gen2-cpg.h | ||
| rcar-gen3-cpg.c | ||
| rcar-gen3-cpg.h | ||
| rcar-usb2-clock-sel.c | ||
| renesas-cpg-mssr.c | ||
| renesas-cpg-mssr.h | ||