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The Amlogic Meson Display controller is composed of several components : DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | vd1 _______ _____________ _________________ | | D |-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________| VIU: Video Input Unit --------------------- The Video Input Unit is in charge of the pixel scanout from the DDR memory. It fetches the frames addresses, stride and parameters from the "Canvas" memory. This part is also in charge of the CSC (Colorspace Conversion). It can handle 2 OSD Planes and 2 Video Planes. VPP: Video Post Processing -------------------------- The Video Post Processing is in charge of the scaling and blending of the various planes into a single pixel stream. There is a special "pre-blending" used by the video planes with a dedicated scaler and a "post-blending" to merge with the OSD Planes. The OSD planes also have a dedicated scaler for one of the OSD. VENC: Video Encoders -------------------- The VENC is composed of the multiple pixel encoders : - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - ENCP : Progressive Video Encoder for HDMI - ENCL : LCD LVDS Encoder The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock tree and provides the scanout clock to the VPP and VIU. The ENCI is connected to a single VDAC for Composite Output. The ENCI and ENCP are connected to an on-chip HDMI Transceiver. This driver is a DRM/KMS driver using the following DRM components : - GEM-CMA - PRIME-CMA - Atomic Modesetting - FBDev-CMA For the following SoCs : - GXBB Family (S905) - GXL Family (S905X, S905D) - GXM Family (S912) The current driver only supports the CVBS PAL/NTSC output modes, but the CRTC/Planes management should support bigger modes. But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in a second time. The Device Tree bindings makes use of the endpoints video interface definitions to connect to the optional CVBS and in the future the HDMI Connector nodes. HDMI Support is planned for a next release. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Video Input Unit */
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#ifndef __MESON_VIU_H
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#define __MESON_VIU_H
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/* OSDx_BLKx_CFG */
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#define OSD_CANVAS_SEL 16
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#define OSD_ENDIANNESS_LE BIT(15)
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#define OSD_ENDIANNESS_BE (0)
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#define OSD_BLK_MODE_422 (0x03 << 8)
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#define OSD_BLK_MODE_16 (0x04 << 8)
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#define OSD_BLK_MODE_32 (0x05 << 8)
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#define OSD_BLK_MODE_24 (0x07 << 8)
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#define OSD_OUTPUT_COLOR_RGB BIT(7)
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#define OSD_OUTPUT_COLOR_YUV (0)
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#define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
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#define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
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#define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
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#define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
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#define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
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#define OSD_INTERLACE_ENABLED BIT(1)
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#define OSD_INTERLACE_ODD BIT(0)
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#define OSD_INTERLACE_EVEN (0)
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/* OSDx_CTRL_STAT */
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#define OSD_ENABLE BIT(21)
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#define OSD_BLK0_ENABLE BIT(0)
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#define OSD_GLOBAL_ALPHA_SHIFT 12
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/* OSDx_CTRL_STAT2 */
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#define OSD_REPLACE_EN BIT(14)
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#define OSD_REPLACE_SHIFT 6
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void meson_viu_init(struct meson_drm *priv);
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#endif /* __MESON_VIU_H */
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