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When reading back from the list registers, we need to perform two actions for level interrupts: 1) clear the soft-pending bit if the interrupt is not pending anymore *in the list register* 2) resample the line level and propagate it to the pending state But these two actions shouldn't be linked, and we should *always* resample the line level, no matter what state is in the list register. Otherwise, we may end-up injecting spurious interrupts that have been already retired. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> |
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| .. | ||
| hyp | ||
| vgic | ||
| arch_timer.c | ||
| pmu.c | ||
| trace.h | ||
| vgic-v2-emul.c | ||
| vgic-v2.c | ||
| vgic-v3-emul.c | ||
| vgic-v3.c | ||
| vgic.c | ||
| vgic.h | ||