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8661970875
An LCD controller driver for nuc900s. The Linux LOGO is just fine and the FB-Test application was ok, too. Signed-off-by: Wang Qiang <rurality.linux@gmail.com> Cc: Wang Zongshun <mcuos.com@gmail.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Krzysztof Helt <krzysztof.h1@poczta.fm> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
254 lines
7.0 KiB
C
254 lines
7.0 KiB
C
/*
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* arch/arm/mach-w90x900/include/mach/regs-serial.h
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*
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* Copyright (c) 2009 Nuvoton technology corporation
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Description:
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* Nuvoton Display, LCM Register list
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* Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11
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*
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*/
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#ifndef __ASM_ARM_W90X900_REGS_LDM_H
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#define __ASM_ARM_W90X900_REGS_LDM_H
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#include <mach/map.h>
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/* Display Controller Control/Status Register */
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#define REG_LCM_DCCS (0x00)
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#define LCM_DCCS_ENG_RST (1 << 0)
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#define LCM_DCCS_VA_EN (1 << 1)
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#define LCM_DCCS_OSD_EN (1 << 2)
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#define LCM_DCCS_DISP_OUT_EN (1 << 3)
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#define LCM_DCCS_DISP_INT_EN (1 << 4)
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#define LCM_DCCS_CMD_ON (1 << 5)
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#define LCM_DCCS_FIELD_INTR (1 << 6)
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#define LCM_DCCS_SINGLE (1 << 7)
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enum LCM_DCCS_VA_SRC {
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LCM_DCCS_VA_SRC_YUV422 = (0 << 8),
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LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8),
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LCM_DCCS_VA_SRC_RGB888 = (2 << 8),
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LCM_DCCS_VA_SRC_RGB666 = (3 << 8),
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LCM_DCCS_VA_SRC_RGB565 = (4 << 8),
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LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8),
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LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8)
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};
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/* Display Device Control Register */
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#define REG_LCM_DEV_CTRL (0x04)
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enum LCM_DEV_CTRL_SWAP_YCbCr {
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LCM_DEV_CTRL_SWAP_UYVY = (0 << 1),
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LCM_DEV_CTRL_SWAP_YUYV = (1 << 1),
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LCM_DEV_CTRL_SWAP_VYUY = (2 << 1),
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LCM_DEV_CTRL_SWAP_YVYU = (3 << 1)
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};
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enum LCM_DEV_CTRL_RGB_SHIFT {
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LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3),
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LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3),
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LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3),
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LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3)
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};
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enum LCM_DEV_CTRL_DEVICE {
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LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5),
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LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5),
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LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5),
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LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5),
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LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5),
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LCM_DEV_CTRL_DEVICE_MPU = (7 << 5)
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};
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#define LCM_DEV_CTRL_LCD_DDA (8)
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#define LCM_DEV_CTRL_YUV2CCIR (16)
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enum LCM_DEV_CTRL_LCD_SEL {
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LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17),
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LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17),
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LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17),
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LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17)
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};
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enum LCM_DEV_CTRL_FAL_D {
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LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19),
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LCM_DEV_CTRL_FAL_D_RISING = (1 << 19),
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};
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enum LCM_DEV_CTRL_H_POL {
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LCM_DEV_CTRL_H_POL_LOW = (0 << 20),
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LCM_DEV_CTRL_H_POL_HIGH = (1 << 20),
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};
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enum LCM_DEV_CTRL_V_POL {
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LCM_DEV_CTRL_V_POL_LOW = (0 << 21),
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LCM_DEV_CTRL_V_POL_HIGH = (1 << 21),
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};
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enum LCM_DEV_CTRL_VR_LACE {
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LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22),
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LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22),
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};
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enum LCM_DEV_CTRL_LACE {
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LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23),
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LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23),
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};
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enum LCM_DEV_CTRL_RGB_SCALE {
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LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24),
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LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24),
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LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24),
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LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24),
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};
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enum LCM_DEV_CTRL_DBWORD {
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LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26),
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LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26),
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};
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enum LCM_DEV_CTRL_MPU68 {
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LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27),
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LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27),
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};
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enum LCM_DEV_CTRL_DE_POL {
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LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28),
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LCM_DEV_CTRL_DE_POL_LOW = (1 << 28),
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};
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#define LCM_DEV_CTRL_CMD16 (29)
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#define LCM_DEV_CTRL_CM16t18 (30)
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#define LCM_DEV_CTRL_CMD_LOW (31)
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/* MPU-Interface LCD Write Command */
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#define REG_LCM_MPU_CMD (0x08)
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/* Interrupt Control/Status Register */
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#define REG_LCM_INT_CS (0x0c)
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#define LCM_INT_CS_DISP_F_EN (1 << 0)
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#define LCM_INT_CS_UNDERRUN_EN (1 << 1)
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#define LCM_INT_CS_BUS_ERROR_INT (1 << 28)
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#define LCM_INT_CS_UNDERRUN_INT (1 << 29)
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#define LCM_INT_CS_DISP_F_STATUS (1 << 30)
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#define LCM_INT_CS_DISP_F_INT (1 << 31)
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/* CRTC Display Size Control Register */
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#define REG_LCM_CRTC_SIZE (0x10)
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#define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16)
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#define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0)
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/* CRTC Display Enable End */
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#define REG_LCM_CRTC_DEND (0x14)
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#define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16)
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#define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0)
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/* CRTC Internal Horizontal Retrace Control Register */
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#define REG_LCM_CRTC_HR (0x18)
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#define LCM_CRTC_HR_EVAL(x) ((x) << 16)
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#define LCM_CRTC_HR_SVAL(x) ((x) << 0)
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/* CRTC Horizontal Sync Control Register */
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#define REG_LCM_CRTC_HSYNC (0x1C)
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#define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30)
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#define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16)
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#define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0)
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/* CRTC Internal Vertical Retrace Control Register */
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#define REG_LCM_CRTC_VR (0x20)
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#define LCM_CRTC_VR_EVAL(x) ((x) << 16)
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#define LCM_CRTC_VR_SVAL(x) ((x) << 0)
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/* Video Stream Frame Buffer-0 Starting Address */
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#define REG_LCM_VA_BADDR0 (0x24)
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/* Video Stream Frame Buffer-1 Starting Address */
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#define REG_LCM_VA_BADDR1 (0x28)
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/* Video Stream Frame Buffer Control Register */
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#define REG_LCM_VA_FBCTRL (0x2C)
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#define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28)
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#define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29)
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#define LCM_VA_FBCTRL_START_BUF (1 << 30)
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#define LCM_VA_FBCTRL_DB_EN (1 << 31)
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/* Video Stream Scaling Control Register */
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#define REG_LCM_VA_SCALE (0x30)
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#define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15)
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#define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15)
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/* Image Stream Active Window Coordinates */
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#define REG_LCM_VA_WIN (0x38)
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/* Image Stream Stuff Pixel */
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#define REG_LCM_VA_STUFF (0x3C)
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/* OSD Window Starting Coordinates */
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#define REG_LCM_OSD_WINS (0x40)
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/* OSD Window Ending Coordinates */
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#define REG_LCM_OSD_WINE (0x44)
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/* OSD Stream Frame Buffer Starting Address */
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#define REG_LCM_OSD_BADDR (0x48)
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/* OSD Stream Frame Buffer Control Register */
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#define REG_LCM_OSD_FBCTRL (0x4c)
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/* OSD Overlay Control Register */
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#define REG_LCM_OSD_OVERLAY (0x50)
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/* OSD Overlay Color-Key Pattern Register */
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#define REG_LCM_OSD_CKEY (0x54)
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/* OSD Overlay Color-Key Mask Register */
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#define REG_LCM_OSD_CMASK (0x58)
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/* OSD Window Skip1 Register */
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#define REG_LCM_OSD_SKIP1 (0x5C)
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/* OSD Window Skip2 Register */
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#define REG_LCM_OSD_SKIP2 (0x60)
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/* OSD horizontal up scaling control register */
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#define REG_LCM_OSD_SCALE (0x64)
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/* MPU Vsync control register */
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#define REG_LCM_MPU_VSYNC (0x68)
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/* Hardware cursor control Register */
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#define REG_LCM_HC_CTRL (0x6C)
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/* Hardware cursot tip point potison on va picture */
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#define REG_LCM_HC_POS (0x70)
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/* Hardware Cursor Window Buffer Control Register */
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#define REG_LCM_HC_WBCTRL (0x74)
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/* Hardware cursor memory base address register */
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#define REG_LCM_HC_BADDR (0x78)
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/* Hardware cursor color ram register mapped to bpp = 0 */
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#define REG_LCM_HC_COLOR0 (0x7C)
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/* Hardware cursor color ram register mapped to bpp = 1 */
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#define REG_LCM_HC_COLOR1 (0x80)
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/* Hardware cursor color ram register mapped to bpp = 2 */
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#define REG_LCM_HC_COLOR2 (0x84)
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/* Hardware cursor color ram register mapped to bpp = 3 */
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#define REG_LCM_HC_COLOR3 (0x88)
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#endif /* __ASM_ARM_W90X900_REGS_LDM_H */
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