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de3e1dd09b
DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX uSDHC internally already uses a fixed optimized timing for DDR50, normally does not require tuning for DDR50 mode. This patch specify a new execute_tuning function for i.MX uSDHC, do not impact i.MX eSDHC. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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