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The flow controller can help CPU to go into suspend mode (powered-down state). When CPU goes into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. For Tegra114, the setting is compatible with Tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* arch/arm/mach-tegra/flowctrl.c
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*
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* functions and macros to control the flowcontroller
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/cpumask.h>
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#include "flowctrl.h"
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#include "iomap.h"
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#include "fuse.h"
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static u8 flowctrl_offset_halt_cpu[] = {
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FLOW_CTRL_HALT_CPU0_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS + 8,
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FLOW_CTRL_HALT_CPU1_EVENTS + 16,
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};
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static u8 flowctrl_offset_cpu_csr[] = {
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FLOW_CTRL_CPU0_CSR,
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FLOW_CTRL_CPU1_CSR,
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FLOW_CTRL_CPU1_CSR + 8,
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FLOW_CTRL_CPU1_CSR + 16,
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};
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static void flowctrl_update(u8 offset, u32 value)
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{
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void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
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writel(value, addr);
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/* ensure the update has reached the flow controller */
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wmb();
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readl_relaxed(addr);
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}
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u32 flowctrl_read_cpu_csr(unsigned int cpuid)
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{
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u8 offset = flowctrl_offset_cpu_csr[cpuid];
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void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
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return readl(addr);
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}
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void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
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}
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void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
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}
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void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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{
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unsigned int reg;
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int i;
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_chip_id) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfe */
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reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
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break;
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case TEGRA30:
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case TEGRA114:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfi */
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reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
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break;
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}
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
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reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
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flowctrl_write_cpu_csr(cpuid, reg);
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for (i = 0; i < num_possible_cpus(); i++) {
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if (i == cpuid)
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continue;
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reg = flowctrl_read_cpu_csr(i);
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reg |= FLOW_CTRL_CSR_EVENT_FLAG;
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reg |= FLOW_CTRL_CSR_INTR_FLAG;
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flowctrl_write_cpu_csr(i, reg);
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}
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}
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void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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{
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unsigned int reg;
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/* Disable powergating via flow controller for CPU0 */
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_chip_id) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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case TEGRA30:
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case TEGRA114:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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}
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reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
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flowctrl_write_cpu_csr(cpuid, reg);
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}
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