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If dual role mode is enabled, when switch u3port0 to device mode, it will affect port id calculation of host(xHCI), specially when host supports multi U2 ports or U3 ports, so need enable its dual role mode, and fix it here. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
481 lines
15 KiB
C
481 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
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*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#ifndef _SSUSB_HW_REGS_H_
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#define _SSUSB_HW_REGS_H_
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/* segment offset of MAC register */
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#define SSUSB_DEV_BASE 0x0000
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#define SSUSB_EPCTL_CSR_BASE 0x0800
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#define SSUSB_USB3_MAC_CSR_BASE 0x1400
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#define SSUSB_USB3_SYS_CSR_BASE 0x1400
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#define SSUSB_USB2_CSR_BASE 0x2400
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/* IPPC register in Infra */
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#define SSUSB_SIFSLV_IPPC_BASE 0x0000
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/* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
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#define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
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#define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
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#define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
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#define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
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#define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
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#define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
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#define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
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#define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
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#define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
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#define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
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#define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
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#define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
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#define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
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#define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
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#define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
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#define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
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#define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
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#define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
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#define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
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#define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
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#define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
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#define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
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#define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
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#define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
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#define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
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#define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
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#define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
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#define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
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#define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
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#define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
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#define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
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#define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
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#define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
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#define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
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#define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
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#define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
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#define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
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#define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
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#define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
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#define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
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#define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
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#define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
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#define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
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#define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
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#define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
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#define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
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#define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
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#define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
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#define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
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#define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
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#define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
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#define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
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#define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
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#define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
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#define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
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#define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
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/*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
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/* U3D_LV1ISR */
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#define EP_CTRL_INTR BIT(5)
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#define MAC2_INTR BIT(4)
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#define DMA_INTR BIT(3)
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#define MAC3_INTR BIT(2)
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#define QMU_INTR BIT(1)
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#define BMU_INTR BIT(0)
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/* U3D_LV1IECR */
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#define LV1IECR_MSK GENMASK(31, 0)
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/* U3D_EPISR */
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#define EPRISR(x) (BIT(16) << (x))
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#define EPTISR(x) (BIT(0) << (x))
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#define EP0ISR BIT(0)
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/* U3D_EP0CSR */
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#define EP0_SENDSTALL BIT(25)
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#define EP0_FIFOFULL BIT(23)
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#define EP0_SENTSTALL BIT(22)
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#define EP0_DPHTX BIT(20)
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#define EP0_DATAEND BIT(19)
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#define EP0_TXPKTRDY BIT(18)
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#define EP0_SETUPPKTRDY BIT(17)
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#define EP0_RXPKTRDY BIT(16)
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#define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
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#define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK)
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#define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
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/* U3D_TX1CSR0 */
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#define TX_DMAREQEN BIT(29)
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#define TX_FIFOFULL BIT(25)
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#define TX_FIFOEMPTY BIT(24)
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#define TX_SENTSTALL BIT(22)
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#define TX_SENDSTALL BIT(21)
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#define TX_TXPKTRDY BIT(16)
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#define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
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#define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK)
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#define TX_W1C_BITS (~(TX_SENTSTALL))
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/* U3D_TX1CSR1 */
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#define TX_MULT(x) (((x) & 0x3) << 22)
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#define TX_MAX_PKT(x) (((x) & 0x3f) << 16)
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#define TX_SLOT(x) (((x) & 0x3f) << 8)
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#define TX_TYPE(x) (((x) & 0x3) << 4)
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#define TX_SS_BURST(x) (((x) & 0xf) << 0)
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/* for TX_TYPE & RX_TYPE */
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#define TYPE_BULK (0x0)
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#define TYPE_INT (0x1)
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#define TYPE_ISO (0x2)
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#define TYPE_MASK (0x3)
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/* U3D_TX1CSR2 */
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#define TX_BINTERVAL(x) (((x) & 0xff) << 24)
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#define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
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#define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
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/* U3D_RX1CSR0 */
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#define RX_DMAREQEN BIT(29)
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#define RX_SENTSTALL BIT(22)
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#define RX_SENDSTALL BIT(21)
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#define RX_RXPKTRDY BIT(16)
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#define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
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#define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK)
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#define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY))
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/* U3D_RX1CSR1 */
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#define RX_MULT(x) (((x) & 0x3) << 22)
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#define RX_MAX_PKT(x) (((x) & 0x3f) << 16)
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#define RX_SLOT(x) (((x) & 0x3f) << 8)
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#define RX_TYPE(x) (((x) & 0x3) << 4)
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#define RX_SS_BURST(x) (((x) & 0xf) << 0)
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/* U3D_RX1CSR2 */
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#define RX_BINTERVAL(x) (((x) & 0xff) << 24)
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#define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
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#define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
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/* U3D_QCR0 */
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#define QMU_RX_CS_EN(x) (BIT(16) << (x))
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#define QMU_TX_CS_EN(x) (BIT(0) << (x))
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#define QMU_CS16B_EN BIT(0)
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/* U3D_QCR1 */
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#define QMU_TX_ZLP(x) (BIT(0) << (x))
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/* U3D_QCR3 */
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#define QMU_RX_COZ(x) (BIT(16) << (x))
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#define QMU_RX_ZLP(x) (BIT(0) << (x))
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/* U3D_TXQHIAR1 */
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/* U3D_RXQHIAR1 */
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#define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
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#define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
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#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
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#define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
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/* U3D_TXQCSR1 */
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/* U3D_RXQCSR1 */
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#define QMU_Q_ACTIVE BIT(15)
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#define QMU_Q_STOP BIT(2)
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#define QMU_Q_RESUME BIT(1)
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#define QMU_Q_START BIT(0)
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/* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
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#define QMU_RX_DONE_INT(x) (BIT(16) << (x))
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#define QMU_TX_DONE_INT(x) (BIT(0) << (x))
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/* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
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#define RXQ_ZLPERR_INT BIT(20)
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#define RXQ_LENERR_INT BIT(18)
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#define RXQ_CSERR_INT BIT(17)
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#define RXQ_EMPTY_INT BIT(16)
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#define TXQ_LENERR_INT BIT(2)
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#define TXQ_CSERR_INT BIT(1)
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#define TXQ_EMPTY_INT BIT(0)
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/* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
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#define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
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#define QMU_TX_CS_ERR(x) (BIT(0) << (x))
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/* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
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#define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
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#define QMU_RX_CS_ERR(x) (BIT(0) << (x))
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/* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
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#define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
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/* U3D_CAP_EPINFO */
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#define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
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#define CAP_TX_EP_NUM(x) ((x) & 0x1f)
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/* U3D_MISC_CTRL */
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#define DMA_ADDR_36BIT BIT(31)
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#define VBUS_ON BIT(1)
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#define VBUS_FRC_EN BIT(0)
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/*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
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#define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
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#define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
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#define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
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#define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
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/*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
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/* U3D_DEVICE_CONF */
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#define DEV_ADDR_MSK GENMASK(30, 24)
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#define DEV_ADDR(x) ((0x7f & (x)) << 24)
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#define HW_USB2_3_SEL BIT(18)
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#define SW_USB2_3_SEL_EN BIT(17)
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#define SW_USB2_3_SEL BIT(16)
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#define SSUSB_DEV_SPEED(x) ((x) & 0x7)
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/* U3D_EP_RST */
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#define EP1_IN_RST BIT(17)
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#define EP1_OUT_RST BIT(1)
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#define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
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#define EP0_RST BIT(0)
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/* U3D_DEV_LINK_INTR_ENABLE */
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/* U3D_DEV_LINK_INTR */
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#define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
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/*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
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#define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
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#define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
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#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
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#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
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/*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
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/* U3D_LTSSM_CTRL */
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#define FORCE_POLLING_FAIL BIT(4)
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#define FORCE_RXDETECT_FAIL BIT(3)
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#define SOFT_U3_EXIT_EN BIT(2)
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#define COMPLIANCE_EN BIT(1)
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#define U1_GO_U2_EN BIT(0)
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/* U3D_USB3_CONFIG */
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#define USB3_EN BIT(0)
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/* U3D_LTSSM_INTR_ENABLE */
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/* U3D_LTSSM_INTR */
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#define U3_RESUME_INTR BIT(18)
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#define U3_LFPS_TMOUT_INTR BIT(17)
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#define VBUS_FALL_INTR BIT(16)
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#define VBUS_RISE_INTR BIT(15)
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#define RXDET_SUCCESS_INTR BIT(14)
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#define EXIT_U3_INTR BIT(13)
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#define EXIT_U2_INTR BIT(12)
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#define EXIT_U1_INTR BIT(11)
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#define ENTER_U3_INTR BIT(10)
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#define ENTER_U2_INTR BIT(9)
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#define ENTER_U1_INTR BIT(8)
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#define ENTER_U0_INTR BIT(7)
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#define RECOVERY_INTR BIT(6)
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#define WARM_RST_INTR BIT(5)
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#define HOT_RST_INTR BIT(4)
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#define LOOPBACK_INTR BIT(3)
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#define COMPLIANCE_INTR BIT(2)
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#define SS_DISABLE_INTR BIT(1)
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#define SS_INACTIVE_INTR BIT(0)
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/*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
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#define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
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#define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
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#define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
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/*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
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/* U3D_LINK_UX_INACT_TIMER */
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#define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)
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#define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
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#define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)
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#define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
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#define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
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/* U3D_LINK_POWER_CONTROL */
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#define SW_U2_ACCEPT_ENABLE BIT(9)
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#define SW_U1_ACCEPT_ENABLE BIT(8)
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#define UX_EXIT BIT(5)
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#define LGO_U3 BIT(4)
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#define LGO_U2 BIT(3)
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#define LGO_U1 BIT(2)
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#define SW_U2_REQUEST_ENABLE BIT(1)
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#define SW_U1_REQUEST_ENABLE BIT(0)
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/* U3D_LINK_ERR_COUNT */
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#define CLR_LINK_ERR_CNT BIT(16)
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#define LINK_ERROR_COUNT GENMASK(15, 0)
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/*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
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#define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
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#define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
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#define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
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#define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
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#define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
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#define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
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#define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
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#define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
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#define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
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/*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
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/* U3D_POWER_MANAGEMENT */
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#define LPM_BESL_STALL BIT(14)
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#define LPM_BESLD_STALL BIT(13)
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#define LPM_RWP BIT(11)
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#define LPM_HRWE BIT(10)
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#define LPM_MODE(x) (((x) & 0x3) << 8)
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#define ISO_UPDATE BIT(7)
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#define SOFT_CONN BIT(6)
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#define HS_ENABLE BIT(5)
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#define RESUME BIT(2)
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#define SUSPENDM_ENABLE BIT(0)
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/* U3D_DEVICE_CONTROL */
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#define DC_HOSTREQ BIT(1)
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#define DC_SESSION BIT(0)
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/* U3D_USB2_TEST_MODE */
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#define U2U3_AUTO_SWITCH BIT(10)
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#define LPM_FORCE_STALL BIT(8)
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#define FIFO_ACCESS BIT(6)
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#define FORCE_FS BIT(5)
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#define FORCE_HS BIT(4)
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#define TEST_PACKET_MODE BIT(3)
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#define TEST_K_MODE BIT(2)
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#define TEST_J_MODE BIT(1)
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#define TEST_SE0_NAK_MODE BIT(0)
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/* U3D_COMMON_USB_INTR_ENABLE */
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/* U3D_COMMON_USB_INTR */
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#define LPM_RESUME_INTR BIT(9)
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#define LPM_INTR BIT(8)
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#define DISCONN_INTR BIT(5)
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#define CONN_INTR BIT(4)
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#define SOF_INTR BIT(3)
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#define RESET_INTR BIT(2)
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#define RESUME_INTR BIT(1)
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#define SUSPEND_INTR BIT(0)
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/* U3D_LINK_RESET_INFO */
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#define WTCHRP_MSK GENMASK(19, 16)
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/* U3D_USB20_LPM_PARAMETER */
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#define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
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#define LPM_BESLCK(x) (((x) & 0xf) << 8)
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#define LPM_BESLDCK(x) (((x) & 0xf) << 4)
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#define LPM_BESL GENMASK(3, 0)
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/* U3D_USB20_MISC_CONTROL */
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#define LPM_U3_ACK_EN BIT(0)
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/*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
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#define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
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#define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
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#define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
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#define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
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#define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
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#define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
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#define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
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#define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
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#define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
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#define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
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#define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
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#define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
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#define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
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#define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
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#define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
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#define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
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#define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
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#define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
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/*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
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/* U3D_SSUSB_IP_PW_CTRL0 */
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#define SSUSB_IP_SW_RST BIT(0)
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/* U3D_SSUSB_IP_PW_CTRL1 */
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#define SSUSB_IP_HOST_PDN BIT(0)
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/* U3D_SSUSB_IP_PW_CTRL2 */
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#define SSUSB_IP_DEV_PDN BIT(0)
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/* U3D_SSUSB_IP_PW_CTRL3 */
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#define SSUSB_IP_PCIE_PDN BIT(0)
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/* U3D_SSUSB_IP_PW_STS1 */
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#define SSUSB_IP_SLEEP_STS BIT(30)
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#define SSUSB_U3_MAC_RST_B_STS BIT(16)
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#define SSUSB_XHCI_RST_B_STS BIT(11)
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#define SSUSB_SYS125_RST_B_STS BIT(10)
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#define SSUSB_REF_RST_B_STS BIT(8)
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#define SSUSB_SYSPLL_STABLE BIT(0)
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/* U3D_SSUSB_IP_PW_STS2 */
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#define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
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/* U3D_SSUSB_OTG_STS */
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#define SSUSB_VBUS_VALID BIT(9)
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/* U3D_SSUSB_OTG_STS_CLR */
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#define SSUSB_VBUS_INTR_CLR BIT(6)
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/* U3D_SSUSB_IP_XHCI_CAP */
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#define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
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#define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
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/* U3D_SSUSB_IP_DEV_CAP */
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#define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
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/* U3D_SSUSB_OTG_INT_EN */
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#define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
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#define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
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/* U3D_SSUSB_U3_CTRL_0P */
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#define SSUSB_U3_PORT_SSP_SPEED BIT(9)
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#define SSUSB_U3_PORT_DUAL_MODE BIT(7)
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#define SSUSB_U3_PORT_HOST_SEL BIT(2)
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#define SSUSB_U3_PORT_PDN BIT(1)
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#define SSUSB_U3_PORT_DIS BIT(0)
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/* U3D_SSUSB_U2_CTRL_0P */
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#define SSUSB_U2_PORT_RG_IDDIG BIT(12)
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#define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
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#define SSUSB_U2_PORT_VBUSVALID BIT(9)
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#define SSUSB_U2_PORT_OTG_SEL BIT(7)
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#define SSUSB_U2_PORT_HOST BIT(2)
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#define SSUSB_U2_PORT_PDN BIT(1)
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#define SSUSB_U2_PORT_DIS BIT(0)
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#define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
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/* U3D_SSUSB_DEV_RST_CTRL */
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#define SSUSB_DEV_SW_RST BIT(0)
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#endif /* _SSUSB_HW_REGS_H_ */
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