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414408d0ee
This patch allows the GIC clockevent device for a CPU to be configured by another CPU. This makes GIC clockevent devices suitable for use as the tick broadcast device, where formerly the GIC timer local to the configuring CPU would have been configured incorrectly. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
381 lines
9.8 KiB
C
381 lines
9.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/bitmap.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <asm/io.h>
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#include <asm/gic.h>
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#include <asm/setup.h>
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#include <asm/traps.h>
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#include <linux/hardirq.h>
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#include <asm-generic/bitops/find.h>
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unsigned int gic_frequency;
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unsigned int gic_present;
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unsigned long _gic_base;
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unsigned int gic_irq_base;
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unsigned int gic_irq_flags[GIC_NUM_INTRS];
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/* The index into this array is the vector # of the interrupt. */
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struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
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static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static struct gic_pending_regs pending_regs[NR_CPUS];
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static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
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cycle_t gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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do {
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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}
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void gic_write_compare(cycle_t cnt)
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{
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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void gic_write_cpu_compare(cycle_t cnt, int cpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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local_irq_restore(flags);
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}
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cycle_t gic_read_compare(void)
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{
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unsigned int hi, lo;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
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return (((cycle_t) hi) << 32) + lo;
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}
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#endif
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unsigned int gic_get_timer_pending(void)
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{
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unsigned int vpe_pending;
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
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GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
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return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
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}
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void gic_bind_eic_interrupt(int irq, int set)
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{
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/* Convert irq vector # to hw int # */
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irq -= GIC_PIN_TO_VEC_OFFSET;
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/* Set irq to use shadow set */
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GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
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}
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void gic_send_ipi(unsigned int intr)
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{
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
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}
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static void gic_eic_irq_dispatch(void)
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{
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unsigned int cause = read_c0_cause();
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int irq;
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irq = (cause & ST0_IM) >> STATUSB_IP2;
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if (irq == 0)
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irq = -1;
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if (irq >= 0)
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do_IRQ(gic_irq_base + irq);
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else
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spurious_interrupt();
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}
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static void __init vpe_local_setup(unsigned int numvpes)
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{
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unsigned long timer_intr = GIC_INT_TMR;
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unsigned long perf_intr = GIC_INT_PERFCTR;
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unsigned int vpe_ctl;
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int i;
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if (cpu_has_veic) {
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/*
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* GIC timer interrupt -> CPU HW Int X (vector X+2) ->
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* map to pin X+2-1 (since GIC adds 1)
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*/
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timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
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/*
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* GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
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* map to pin X+2-1 (since GIC adds 1)
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*/
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perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
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}
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/*
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* Setup the default performance counter timer interrupts
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* for all VPEs
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*/
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for (i = 0; i < numvpes; i++) {
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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/* Are Interrupts locally routable? */
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GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
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if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
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GIC_MAP_TO_PIN_MSK | timer_intr);
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if (cpu_has_veic) {
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set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
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gic_eic_irq_dispatch);
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gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
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}
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if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
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GIC_MAP_TO_PIN_MSK | perf_intr);
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if (cpu_has_veic) {
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set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
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gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
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}
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}
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}
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unsigned int gic_compare_int(void)
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{
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unsigned int pending;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
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if (pending & GIC_VPE_PEND_CMP_MSK)
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return 1;
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else
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return 0;
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}
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unsigned int gic_get_int(void)
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{
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unsigned int i;
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unsigned long *pending, *intrmask, *pcpu_mask;
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unsigned long *pending_abs, *intrmask_abs;
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/* Get per-cpu bitmaps */
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pending = pending_regs[smp_processor_id()].pending;
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intrmask = intrmask_regs[smp_processor_id()].intrmask;
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pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
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pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_PEND_31_0_OFS);
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intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_MASK_31_0_OFS);
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for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
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GICREAD(*pending_abs, pending[i]);
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GICREAD(*intrmask_abs, intrmask[i]);
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pending_abs++;
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intrmask_abs++;
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}
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bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
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bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
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return find_first_bit(pending, GIC_NUM_INTRS);
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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GIC_SET_INTR_MASK(d->irq - gic_irq_base);
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}
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#ifdef CONFIG_SMP
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static DEFINE_SPINLOCK(gic_lock);
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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bool force)
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{
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unsigned int irq = (d->irq - gic_irq_base);
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cpumask_t tmp = CPU_MASK_NONE;
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unsigned long flags;
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int i;
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cpumask_and(&tmp, cpumask, cpu_online_mask);
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if (cpus_empty(tmp))
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return -1;
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/* Assumption : cpumask refers to a single CPU */
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spin_lock_irqsave(&gic_lock, flags);
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/* Re-route this IRQ */
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GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
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/* Update the pcpu_masks */
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for (i = 0; i < NR_CPUS; i++)
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clear_bit(irq, pcpu_masks[i].pcpu_mask);
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set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
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cpumask_copy(d->affinity, cpumask);
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spin_unlock_irqrestore(&gic_lock, flags);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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#endif
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static struct irq_chip gic_irq_controller = {
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.name = "MIPS GIC",
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.irq_ack = gic_irq_ack,
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.irq_mask = gic_mask_irq,
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.irq_mask_ack = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_finish_irq,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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};
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static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
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unsigned int pin, unsigned int polarity, unsigned int trigtype,
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unsigned int flags)
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{
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struct gic_shared_intr_map *map_ptr;
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/* Setup Intr to Pin mapping */
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if (pin & GIC_MAP_TO_NMI_MSK) {
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
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/* FIXME: hack to route NMI to all cpu's */
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for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
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GICWRITE(GIC_REG_ADDR(SHARED,
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GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
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0xffffffff);
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}
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} else {
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
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GIC_MAP_TO_PIN_MSK | pin);
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/* Setup Intr to CPU mapping */
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GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
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if (cpu_has_veic) {
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set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
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gic_eic_irq_dispatch);
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map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
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if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
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BUG();
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map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
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}
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}
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/* Setup Intr Polarity */
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GIC_SET_POLARITY(intr, polarity);
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/* Setup Intr Trigger Type */
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GIC_SET_TRIGGER(intr, trigtype);
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/* Init Intr Masks */
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GIC_CLR_INTR_MASK(intr);
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/* Initialise per-cpu Interrupt software masks */
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if (flags & GIC_FLAG_IPI)
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set_bit(intr, pcpu_masks[cpu].pcpu_mask);
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if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
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GIC_SET_INTR_MASK(intr);
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if (trigtype == GIC_TRIG_EDGE)
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gic_irq_flags[intr] |= GIC_TRIG_EDGE;
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}
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static void __init gic_basic_init(int numintrs, int numvpes,
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struct gic_intr_map *intrmap, int mapsize)
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{
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unsigned int i, cpu;
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unsigned int pin_offset = 0;
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board_bind_eic_interrupt = &gic_bind_eic_interrupt;
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/* Setup defaults */
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for (i = 0; i < numintrs; i++) {
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GIC_SET_POLARITY(i, GIC_POL_POS);
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GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
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GIC_CLR_INTR_MASK(i);
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if (i < GIC_NUM_INTRS) {
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gic_irq_flags[i] = 0;
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gic_shared_intr_map[i].num_shared_intr = 0;
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gic_shared_intr_map[i].local_intr_mask = 0;
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}
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}
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/*
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* In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
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* one because the GIC will add one (since 0=no intr).
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*/
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if (cpu_has_veic)
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pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
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/* Setup specifics */
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for (i = 0; i < mapsize; i++) {
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cpu = intrmap[i].cpunum;
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if (cpu == GIC_UNUSED)
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continue;
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if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
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continue;
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gic_setup_intr(i,
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intrmap[i].cpunum,
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intrmap[i].pin + pin_offset,
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intrmap[i].polarity,
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intrmap[i].trigtype,
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intrmap[i].flags);
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}
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vpe_local_setup(numvpes);
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}
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void __init gic_init(unsigned long gic_base_addr,
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unsigned long gic_addrspace_size,
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struct gic_intr_map *intr_map, unsigned int intr_map_size,
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unsigned int irqbase)
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{
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unsigned int gicconfig;
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int numvpes, numintrs;
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_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
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gic_addrspace_size);
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gic_irq_base = irqbase;
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GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
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numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
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GIC_SH_CONFIG_NUMINTRS_SHF;
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numintrs = ((numintrs + 1) * 8);
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numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
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GIC_SH_CONFIG_NUMVPES_SHF;
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numvpes = numvpes + 1;
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gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
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gic_platform_init(numintrs, &gic_irq_controller);
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}
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