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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
336 lines
8.5 KiB
C
336 lines
8.5 KiB
C
/* $Id: fpu.c,v 1.4 2004/01/13 05:52:11 kkojima Exp $
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*
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* linux/arch/sh/kernel/fpu.c
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*
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* Save/restore floating point context for signal handlers.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
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*
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* FIXME! These routines can be optimized in big endian case.
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*/
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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/* The PR (precision) bit in the FP Status Register must be clear when
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* an frchg instruction is executed, otherwise the instruction is undefined.
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* Executing frchg with PR set causes a trap on some SH4 implementations.
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*/
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#define FPSCR_RCHG 0x00000000
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/*
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* Save FPU registers onto task structure.
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* Assume called with FPU enabled (SR.FD=0).
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*/
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void
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save_fpu(struct task_struct *tsk, struct pt_regs *regs)
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{
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unsigned long dummy;
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clear_tsk_thread_flag(tsk, TIF_USEDFPU);
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enable_fpu();
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asm volatile("sts.l fpul, @-%0\n\t"
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"sts.l fpscr, @-%0\n\t"
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"lds %2, fpscr\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"lds %3, fpscr\n\t"
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: "=r" (dummy)
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: "0" ((char *)(&tsk->thread.fpu.hard.status)),
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"r" (FPSCR_RCHG),
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"r" (FPSCR_INIT)
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: "memory");
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disable_fpu();
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release_fpu(regs);
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}
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static void
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restore_fpu(struct task_struct *tsk)
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{
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unsigned long dummy;
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enable_fpu();
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asm volatile("lds %2, fpscr\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"lds.l @%0+, fpscr\n\t"
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"lds.l @%0+, fpul\n\t"
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: "=r" (dummy)
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: "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
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: "memory");
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disable_fpu();
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}
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using
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* has the property that no matter wether considered as single or as
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* double precission represents signaling NANS.
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*/
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static void
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fpu_init(void)
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{
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enable_fpu();
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asm volatile("lds %0, fpul\n\t"
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"lds %1, fpscr\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"lds %2, fpscr\n\t"
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: /* no output */
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: "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
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disable_fpu();
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}
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/**
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* denormal_to_double - Given denormalized float number,
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* store double float
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*
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* @fpu: Pointer to sh_fpu_hard structure
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* @n: Index to FP register
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*/
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static void
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denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
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{
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unsigned long du, dl;
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unsigned long x = fpu->fpul;
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int exp = 1023 - 126;
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if (x != 0 && (x & 0x7f800000) == 0) {
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du = (x & 0x80000000);
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while ((x & 0x00800000) == 0) {
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x <<= 1;
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exp--;
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}
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x &= 0x007fffff;
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du |= (exp << 20) | (x >> 3);
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dl = x << 29;
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fpu->fp_regs[n] = du;
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fpu->fp_regs[n+1] = dl;
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}
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}
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/**
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* ieee_fpe_handler - Handle denormalized number exception
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*
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* @regs: Pointer to register structure
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*
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* Returns 1 when it's handled (should not cause exception).
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*/
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static int
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ieee_fpe_handler (struct pt_regs *regs)
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{
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unsigned short insn = *(unsigned short *) regs->pc;
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unsigned short finsn;
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unsigned long nextpc;
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int nib[4] = {
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(insn >> 12) & 0xf,
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(insn >> 8) & 0xf,
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(insn >> 4) & 0xf,
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insn & 0xf};
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if (nib[0] == 0xb ||
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(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
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regs->pr = regs->pc + 4;
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if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
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nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
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finsn = *(unsigned short *) (regs->pc + 2);
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} else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
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if (regs->sr & 1)
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nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
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else
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nextpc = regs->pc + 4;
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finsn = *(unsigned short *) (regs->pc + 2);
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} else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
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if (regs->sr & 1)
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nextpc = regs->pc + 4;
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else
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nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
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finsn = *(unsigned short *) (regs->pc + 2);
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} else if (nib[0] == 0x4 && nib[3] == 0xb &&
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(nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
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nextpc = regs->regs[nib[1]];
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finsn = *(unsigned short *) (regs->pc + 2);
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} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
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(nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
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nextpc = regs->pc + 4 + regs->regs[nib[1]];
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finsn = *(unsigned short *) (regs->pc + 2);
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} else if (insn == 0x000b) { /* rts */
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nextpc = regs->pr;
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finsn = *(unsigned short *) (regs->pc + 2);
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} else {
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nextpc = regs->pc + 2;
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finsn = insn;
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}
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if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
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struct task_struct *tsk = current;
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save_fpu(tsk, regs);
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if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) {
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/* FPU error */
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denormal_to_double (&tsk->thread.fpu.hard,
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(finsn >> 8) & 0xf);
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tsk->thread.fpu.hard.fpscr &=
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~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
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grab_fpu(regs);
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restore_fpu(tsk);
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set_tsk_thread_flag(tsk, TIF_USEDFPU);
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} else {
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tsk->thread.trap_no = 11;
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tsk->thread.error_code = 0;
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force_sig(SIGFPE, tsk);
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}
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regs->pc = nextpc;
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return 1;
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}
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return 0;
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}
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asmlinkage void
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do_fpu_error(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7,
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struct pt_regs regs)
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{
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struct task_struct *tsk = current;
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if (ieee_fpe_handler (®s))
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return;
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regs.pc += 2;
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save_fpu(tsk, ®s);
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tsk->thread.trap_no = 11;
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tsk->thread.error_code = 0;
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force_sig(SIGFPE, tsk);
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}
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asmlinkage void
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do_fpu_state_restore(unsigned long r4, unsigned long r5, unsigned long r6,
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unsigned long r7, struct pt_regs regs)
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{
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struct task_struct *tsk = current;
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grab_fpu(®s);
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if (!user_mode(®s)) {
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printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
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return;
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}
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if (used_math()) {
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/* Using the FPU again. */
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restore_fpu(tsk);
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} else {
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/* First time FPU user. */
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fpu_init();
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set_used_math();
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}
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set_tsk_thread_flag(tsk, TIF_USEDFPU);
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}
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