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- A series of commits to make the MSR derived CPU and TSC frequency more accurate. It turned out that the frequency tables which have been taken from the SDM are inaccurate because the SDM provides truncated and rounded values, e.g. 83.3Mhz (83.3333...) or 116.7Mhz (116.6666...). This causes time drift in the range of ~1 second per hour (20-30 seconds per day). On some of these SoCs it's not possible to recalibrate the TSC because there is no reference (PIT, HPET) available. With some reverse engineering it was established that the possible frequencies are derived from the base clock with fixed multiplier / divider pairs. For the CPU models which have a known crystal frequency the kernel now uses multiplier / divider pairs which bring the frequencies closer to reality and fix the observed time drift issues. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAl6CApYTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoRM4D/9/lgBQQQ+xilpYHLv4lk5ukmkrLEjt NqL0dZKthd2v4VoAViCZqCYUSuxmo9uGPCxC0Ol7MMB2mUHXrwPn5q2wwcHSE830 KQv8Dk9tCVeJMMTMk2s5t4QBYEHD95+ueObKK1sofz0NkQW3ea+cpRCh4jt2lrnw X7uT5rSHk87B1VYMPWzELsBEeqan9kUbvbe9se7My5utesOZumn4gj9rmO/5y9Vc rNuwGEZX8RpQAZZmfEJ00r5iA+VTdWyQ4rhktlQeeIdb4y4axjxMsWQIuaggjdyn oRA2vZnoc4+IqNUUBvj1q1D3RETwyf3WT+nxiYUdb3VuSh1o7he5MTzgznKzThnU s+ViOPXbfzrfUUW8dlk6zd5yovmIuQNb0Xk05USqAB3gVQS1fYPnyy+pb9dFDnnB 0zEq3RAQVCb/bkyWQ0JemgHXda3WTABZRCR812L2e+WZD6KjlqySkdeJJ+kxzQwN 6FRNrdtl+8ULy6SlWIC8y0yuVdSIFfgNSm+5HZMrw8VbqJp1ZVpTvKQ+xczjOunn z9y24IC1IlhtDsTMzIU0LHhgwhVGcohdTNbu3yX4hVQ7EgQOQPVE/XGM5RdjiXzq bD5j+PCntjoE7hnnxsPnuhDs9ZqNptTo4UevMwTL6rKAgJaPMAc9PB5LqdUynAEx hpkkMFGU7BSBDw== =9eX1 -----END PGP SIGNATURE----- Merge tag 'x86-timers-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 timer updates from Thomas Gleixner: "A series of commits to make the MSR derived CPU and TSC frequency more accurate. It turned out that the frequency tables which have been taken from the SDM are inaccurate because the SDM provides truncated and rounded values, e.g. 83.3Mhz (83.3333...) or 116.7Mhz (116.6666...). This causes time drift in the range of ~1 second per hour (20-30 seconds per day). On some of these SoCs it's not possible to recalibrate the TSC because there is no reference (PIT, HPET) available. With some reverse engineering it was established that the possible frequencies are derived from the base clock with fixed multiplier / divider pairs. For the CPU models which have a known crystal frequency the kernel now uses multiplier / divider pairs which bring the frequencies closer to reality and fix the observed time drift issues" * tag 'x86-timers-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tsc_msr: Make MSR derived TSC frequency more accurate x86/tsc_msr: Fix MSR_FSB_FREQ mask for Cherry Trail devices x86/tsc_msr: Use named struct initializers |
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