mirror of
https://github.com/torvalds/linux.git
synced 2024-11-16 00:52:01 +00:00
588ab3f9af
- Initial page table creation reworked to avoid breaking large block mappings (huge pages) into smaller ones. The ARM architecture requires break-before-make in such cases to avoid TLB conflicts but that's not always possible on live page tables - Kernel virtual memory layout: the kernel image is no longer linked to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of the vmalloc space, allowing the kernel to be loaded (nearly) anywhere in physical RAM - Kernel ASLR: position independent kernel Image and modules being randomly mapped in the vmalloc space with the randomness is provided by UEFI (efi_get_random_bytes() patches merged via the arm64 tree, acked by Matt Fleming) - Implement relative exception tables for arm64, required by KASLR (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but actual x86 conversion to deferred to 4.7 because of the merge dependencies) - Support for the User Access Override feature of ARMv8.2: this allows uaccess functions (get_user etc.) to be implemented using LDTR/STTR instructions. Such instructions, when run by the kernel, perform unprivileged accesses adding an extra level of protection. The set_fs() macro is used to "upgrade" such instruction to privileged accesses via the UAO bit - Half-precision floating point support (part of ARMv8.2) - Optimisations for CPUs with or without a hardware prefetcher (using run-time code patching) - copy_page performance improvement to deal with 128 bytes at a time - Sanity checks on the CPU capabilities (via CPUID) to prevent incompatible secondary CPUs from being brought up (e.g. weird big.LITTLE configurations) - valid_user_regs() reworked for better sanity check of the sigcontext information (restored pstate information) - ACPI parking protocol implementation - CONFIG_DEBUG_RODATA enabled by default - VDSO code marked as read-only - DEBUG_PAGEALLOC support - ARCH_HAS_UBSAN_SANITIZE_ALL enabled - Erratum workaround Cavium ThunderX SoC - set_pte_at() fix for PROT_NONE mappings - Code clean-ups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW6u95AAoJEGvWsS0AyF7xMyoP/3x2O6bgreSQ84BdO4JChN4+ RQ9OVdX8u2ItO9sgaCY2AA6KoiBuEjGmPl/XRuK0I7DpODTtRjEXQHuNNhz8AelC hn4AEVqamY6Z5BzHFIjs8G9ydEbq+OXcKWEdwSsBhP/cMvI7ss3dps1f5iNPT5Vv 50E/kUz+aWYy7pKlB18VDV7TUOA3SuYuGknWV8+bOY5uPb8hNT3Y3fHOg/EuNNN3 DIuYH1V7XQkXtF+oNVIGxzzJCXULBE7egMcWAm1ydSOHK0JwkZAiL7OhI7ceVD0x YlDxBnqmi4cgzfBzTxITAhn3OParwN6udQprdF1WGtFF6fuY2eRDSH/L/iZoE4DY OulL951OsBtF8YC3+RKLk908/0bA2Uw8ftjCOFJTYbSnZBj1gWK41VkCYMEXiHQk EaN8+2Iw206iYIoyvdjGCLw7Y0oakDoVD9vmv12SOaHeQljTkjoN8oIlfjjKTeP7 3AXj5v9BDMDVh40nkVayysRNvqe48Kwt9Wn0rhVTLxwdJEiFG/OIU6HLuTkretdN dcCNFSQrRieSFHpBK9G0vKIpIss1ZwLm8gjocVXH7VK4Mo/TNQe4p2/wAF29mq4r xu1UiXmtU3uWxiqZnt72LOYFCarQ0sFA5+pMEvF5W+NrVB0wGpXhcwm+pGsIi4IM LepccTgykiUBqW5TRzPz =/oS+ -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: "Here are the main arm64 updates for 4.6. There are some relatively intrusive changes to support KASLR, the reworking of the kernel virtual memory layout and initial page table creation. Summary: - Initial page table creation reworked to avoid breaking large block mappings (huge pages) into smaller ones. The ARM architecture requires break-before-make in such cases to avoid TLB conflicts but that's not always possible on live page tables - Kernel virtual memory layout: the kernel image is no longer linked to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of the vmalloc space, allowing the kernel to be loaded (nearly) anywhere in physical RAM - Kernel ASLR: position independent kernel Image and modules being randomly mapped in the vmalloc space with the randomness is provided by UEFI (efi_get_random_bytes() patches merged via the arm64 tree, acked by Matt Fleming) - Implement relative exception tables for arm64, required by KASLR (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but actual x86 conversion to deferred to 4.7 because of the merge dependencies) - Support for the User Access Override feature of ARMv8.2: this allows uaccess functions (get_user etc.) to be implemented using LDTR/STTR instructions. Such instructions, when run by the kernel, perform unprivileged accesses adding an extra level of protection. The set_fs() macro is used to "upgrade" such instruction to privileged accesses via the UAO bit - Half-precision floating point support (part of ARMv8.2) - Optimisations for CPUs with or without a hardware prefetcher (using run-time code patching) - copy_page performance improvement to deal with 128 bytes at a time - Sanity checks on the CPU capabilities (via CPUID) to prevent incompatible secondary CPUs from being brought up (e.g. weird big.LITTLE configurations) - valid_user_regs() reworked for better sanity check of the sigcontext information (restored pstate information) - ACPI parking protocol implementation - CONFIG_DEBUG_RODATA enabled by default - VDSO code marked as read-only - DEBUG_PAGEALLOC support - ARCH_HAS_UBSAN_SANITIZE_ALL enabled - Erratum workaround Cavium ThunderX SoC - set_pte_at() fix for PROT_NONE mappings - Code clean-ups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (99 commits) arm64: kasan: Fix zero shadow mapping overriding kernel image shadow arm64: kasan: Use actual memory node when populating the kernel image shadow arm64: Update PTE_RDONLY in set_pte_at() for PROT_NONE permission arm64: Fix misspellings in comments. arm64: efi: add missing frame pointer assignment arm64: make mrs_s prefixing implicit in read_cpuid arm64: enable CONFIG_DEBUG_RODATA by default arm64: Rework valid_user_regs arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly arm64: KVM: Move kvm_call_hyp back to its original localtion arm64: mm: treat memstart_addr as a signed quantity arm64: mm: list kernel sections in order arm64: lse: deal with clobbered IP registers after branch via PLT arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR arm64: kconfig: add submenu for 8.2 architectural features arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postboot arm64: Add support for Half precision floating point arm64: Remove fixmap include fragility arm64: Add workaround for Cavium erratum 27456 arm64: mm: Mark .rodata as RO ...
894 lines
20 KiB
C
894 lines
20 KiB
C
/*
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* SMP initialisation and IPI support
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* Based on arch/arm/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/cache.h>
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#include <linux/profile.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/err.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <linux/percpu.h>
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#include <linux/clockchips.h>
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#include <linux/completion.h>
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#include <linux/of.h>
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#include <linux/irq_work.h>
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#include <asm/alternative.h>
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpu_ops.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/smp_plat.h>
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#include <asm/sections.h>
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#include <asm/tlbflush.h>
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#include <asm/ptrace.h>
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#include <asm/virt.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/ipi.h>
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/*
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* as from 2.5, kernels no longer have an init_tasks structure
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* so we need some other way of telling a new secondary core
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* where to place its SVC stack
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*/
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struct secondary_data secondary_data;
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/* Number of CPUs which aren't online, but looping in kernel text. */
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int cpus_stuck_in_kernel;
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enum ipi_msg_type {
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IPI_RESCHEDULE,
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IPI_CALL_FUNC,
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IPI_CPU_STOP,
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IPI_TIMER,
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IPI_IRQ_WORK,
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IPI_WAKEUP
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};
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#ifdef CONFIG_HOTPLUG_CPU
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static int op_cpu_kill(unsigned int cpu);
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#else
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static inline int op_cpu_kill(unsigned int cpu)
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{
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return -ENOSYS;
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}
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#endif
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/*
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* Boot a secondary CPU, and assign it the specified idle task.
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* This also gives us the initial stack to use for this CPU.
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*/
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static int boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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if (cpu_ops[cpu]->cpu_boot)
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return cpu_ops[cpu]->cpu_boot(cpu);
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return -EOPNOTSUPP;
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}
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static DECLARE_COMPLETION(cpu_running);
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int __cpu_up(unsigned int cpu, struct task_struct *idle)
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{
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int ret;
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long status;
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/*
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* We need to tell the secondary core where to find its stack and the
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* page tables.
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*/
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secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
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update_cpu_boot_status(CPU_MMU_OFF);
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__flush_dcache_area(&secondary_data, sizeof(secondary_data));
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/*
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* Now bring the CPU into our world.
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*/
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ret = boot_secondary(cpu, idle);
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if (ret == 0) {
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/*
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* CPU was successfully started, wait for it to come online or
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* time out.
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*/
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wait_for_completion_timeout(&cpu_running,
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msecs_to_jiffies(1000));
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if (!cpu_online(cpu)) {
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pr_crit("CPU%u: failed to come online\n", cpu);
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ret = -EIO;
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}
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} else {
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pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
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}
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secondary_data.stack = NULL;
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status = READ_ONCE(secondary_data.status);
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if (ret && status) {
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if (status == CPU_MMU_OFF)
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status = READ_ONCE(__early_cpu_boot_status);
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switch (status) {
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default:
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pr_err("CPU%u: failed in unknown state : 0x%lx\n",
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cpu, status);
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break;
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case CPU_KILL_ME:
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if (!op_cpu_kill(cpu)) {
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pr_crit("CPU%u: died during early boot\n", cpu);
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break;
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}
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/* Fall through */
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pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
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case CPU_STUCK_IN_KERNEL:
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pr_crit("CPU%u: is stuck in kernel\n", cpu);
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cpus_stuck_in_kernel++;
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break;
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case CPU_PANIC_KERNEL:
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panic("CPU%u detected unsupported configuration\n", cpu);
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}
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}
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return ret;
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}
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static void smp_store_cpu_info(unsigned int cpuid)
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{
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store_cpu_topology(cpuid);
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}
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/*
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* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack, but a set of temporary page tables.
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*/
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asmlinkage void secondary_start_kernel(void)
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{
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struct mm_struct *mm = &init_mm;
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unsigned int cpu = smp_processor_id();
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/*
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* All kernel threads share the same mm context; grab a
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* reference and switch to it.
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*/
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
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/*
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* TTBR0 is only used for the identity mapping at this stage. Make it
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* point to zero page to avoid speculatively fetching new entries.
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*/
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cpu_uninstall_idmap();
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preempt_disable();
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trace_hardirqs_off();
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/*
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* If the system has established the capabilities, make sure
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* this CPU ticks all of those. If it doesn't, the CPU will
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* fail to come online.
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*/
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verify_local_cpu_capabilities();
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if (cpu_ops[cpu]->cpu_postboot)
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cpu_ops[cpu]->cpu_postboot();
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/*
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* Log the CPU info before it is marked online and might get read.
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*/
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cpuinfo_store_cpu();
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/*
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* Enable GIC and timers.
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*/
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notify_cpu_starting(cpu);
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smp_store_cpu_info(cpu);
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/*
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* OK, now it's safe to let the boot CPU continue. Wait for
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* the CPU migration code to notice that the CPU is online
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* before we continue.
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*/
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pr_info("CPU%u: Booted secondary processor [%08x]\n",
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cpu, read_cpuid_id());
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update_cpu_boot_status(CPU_BOOT_SUCCESS);
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/* Make sure the status update is visible before we complete */
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smp_wmb();
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set_cpu_online(cpu, true);
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complete(&cpu_running);
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local_dbg_enable();
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local_irq_enable();
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local_async_enable();
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/*
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* OK, it's off to the idle thread for us
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*/
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int op_cpu_disable(unsigned int cpu)
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{
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/*
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* If we don't have a cpu_die method, abort before we reach the point
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* of no return. CPU0 may not have an cpu_ops, so test for it.
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*/
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if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
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return -EOPNOTSUPP;
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/*
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* We may need to abort a hot unplug for some other mechanism-specific
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* reason.
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*/
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if (cpu_ops[cpu]->cpu_disable)
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return cpu_ops[cpu]->cpu_disable(cpu);
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return 0;
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}
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/*
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* __cpu_disable runs on the processor to be shutdown.
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*/
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int __cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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int ret;
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ret = op_cpu_disable(cpu);
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if (ret)
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return ret;
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/*
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* Take this CPU offline. Once we clear this, we can't return,
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* and we must not schedule until we're ready to give up the cpu.
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*/
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set_cpu_online(cpu, false);
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/*
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* OK - migrate IRQs away from this CPU
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*/
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irq_migrate_all_off_this_cpu();
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return 0;
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}
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static int op_cpu_kill(unsigned int cpu)
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{
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/*
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* If we have no means of synchronising with the dying CPU, then assume
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* that it is really dead. We can only wait for an arbitrary length of
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* time and hope that it's dead, so let's skip the wait and just hope.
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*/
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if (!cpu_ops[cpu]->cpu_kill)
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return 0;
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return cpu_ops[cpu]->cpu_kill(cpu);
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}
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/*
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* called on the thread which is asking for a CPU to be shutdown -
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* waits until shutdown has completed, or it is timed out.
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*/
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void __cpu_die(unsigned int cpu)
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{
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int err;
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if (!cpu_wait_death(cpu, 5)) {
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pr_crit("CPU%u: cpu didn't die\n", cpu);
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return;
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}
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pr_notice("CPU%u: shutdown\n", cpu);
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/*
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* Now that the dying CPU is beyond the point of no return w.r.t.
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* in-kernel synchronisation, try to get the firwmare to help us to
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* verify that it has really left the kernel before we consider
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* clobbering anything it might still be using.
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*/
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err = op_cpu_kill(cpu);
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if (err)
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pr_warn("CPU%d may not have shut down cleanly: %d\n",
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cpu, err);
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}
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/*
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* Called from the idle thread for the CPU which has been shutdown.
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*
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* Note that we disable IRQs here, but do not re-enable them
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* before returning to the caller. This is also the behaviour
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* of the other hotplug-cpu capable cores, so presumably coming
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* out of idle fixes this.
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*/
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void cpu_die(void)
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{
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unsigned int cpu = smp_processor_id();
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idle_task_exit();
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local_irq_disable();
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/* Tell __cpu_die() that this CPU is now safe to dispose of */
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(void)cpu_report_death();
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/*
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* Actually shutdown the CPU. This must never fail. The specific hotplug
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* mechanism must perform all required cache maintenance to ensure that
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* no dirty lines are lost in the process of shutting down the CPU.
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*/
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cpu_ops[cpu]->cpu_die(cpu);
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BUG();
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}
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#endif
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/*
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* Kill the calling secondary CPU, early in bringup before it is turned
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* online.
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*/
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void cpu_die_early(void)
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{
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int cpu = smp_processor_id();
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pr_crit("CPU%d: will not boot\n", cpu);
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/* Mark this CPU absent */
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set_cpu_present(cpu, 0);
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#ifdef CONFIG_HOTPLUG_CPU
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update_cpu_boot_status(CPU_KILL_ME);
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/* Check if we can park ourselves */
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if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
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cpu_ops[cpu]->cpu_die(cpu);
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#endif
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update_cpu_boot_status(CPU_STUCK_IN_KERNEL);
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cpu_park_loop();
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}
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static void __init hyp_mode_check(void)
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{
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if (is_hyp_mode_available())
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pr_info("CPU: All CPU(s) started at EL2\n");
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else if (is_hyp_mode_mismatched())
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WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC,
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"CPU: CPUs started in inconsistent modes");
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else
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pr_info("CPU: All CPU(s) started at EL1\n");
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
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setup_cpu_features();
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hyp_mode_check();
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apply_alternatives_all();
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}
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void __init smp_prepare_boot_cpu(void)
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{
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cpuinfo_store_boot_cpu();
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set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
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}
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static u64 __init of_get_cpu_mpidr(struct device_node *dn)
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{
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const __be32 *cell;
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u64 hwid;
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/*
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* A cpu node with missing "reg" property is
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* considered invalid to build a cpu_logical_map
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* entry.
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*/
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cell = of_get_property(dn, "reg", NULL);
|
|
if (!cell) {
|
|
pr_err("%s: missing reg property\n", dn->full_name);
|
|
return INVALID_HWID;
|
|
}
|
|
|
|
hwid = of_read_number(cell, of_n_addr_cells(dn));
|
|
/*
|
|
* Non affinity bits must be set to 0 in the DT
|
|
*/
|
|
if (hwid & ~MPIDR_HWID_BITMASK) {
|
|
pr_err("%s: invalid reg property\n", dn->full_name);
|
|
return INVALID_HWID;
|
|
}
|
|
return hwid;
|
|
}
|
|
|
|
/*
|
|
* Duplicate MPIDRs are a recipe for disaster. Scan all initialized
|
|
* entries and check for duplicates. If any is found just ignore the
|
|
* cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
|
|
* matching valid MPIDR values.
|
|
*/
|
|
static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
|
|
if (cpu_logical_map(i) == hwid)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* Initialize cpu operations for a logical cpu and
|
|
* set it in the possible mask on success
|
|
*/
|
|
static int __init smp_cpu_setup(int cpu)
|
|
{
|
|
if (cpu_read_ops(cpu))
|
|
return -ENODEV;
|
|
|
|
if (cpu_ops[cpu]->cpu_init(cpu))
|
|
return -ENODEV;
|
|
|
|
set_cpu_possible(cpu, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool bootcpu_valid __initdata;
|
|
static unsigned int cpu_count = 1;
|
|
|
|
#ifdef CONFIG_ACPI
|
|
/*
|
|
* acpi_map_gic_cpu_interface - parse processor MADT entry
|
|
*
|
|
* Carry out sanity checks on MADT processor entry and initialize
|
|
* cpu_logical_map on success
|
|
*/
|
|
static void __init
|
|
acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
|
|
{
|
|
u64 hwid = processor->arm_mpidr;
|
|
|
|
if (!(processor->flags & ACPI_MADT_ENABLED)) {
|
|
pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
|
|
return;
|
|
}
|
|
|
|
if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
|
|
pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
|
|
return;
|
|
}
|
|
|
|
if (is_mpidr_duplicate(cpu_count, hwid)) {
|
|
pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
|
|
return;
|
|
}
|
|
|
|
/* Check if GICC structure of boot CPU is available in the MADT */
|
|
if (cpu_logical_map(0) == hwid) {
|
|
if (bootcpu_valid) {
|
|
pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
|
|
hwid);
|
|
return;
|
|
}
|
|
bootcpu_valid = true;
|
|
return;
|
|
}
|
|
|
|
if (cpu_count >= NR_CPUS)
|
|
return;
|
|
|
|
/* map the logical cpu id to cpu MPIDR */
|
|
cpu_logical_map(cpu_count) = hwid;
|
|
|
|
/*
|
|
* Set-up the ACPI parking protocol cpu entries
|
|
* while initializing the cpu_logical_map to
|
|
* avoid parsing MADT entries multiple times for
|
|
* nothing (ie a valid cpu_logical_map entry should
|
|
* contain a valid parking protocol data set to
|
|
* initialize the cpu if the parking protocol is
|
|
* the only available enable method).
|
|
*/
|
|
acpi_set_mailbox_entry(cpu_count, processor);
|
|
|
|
cpu_count++;
|
|
}
|
|
|
|
static int __init
|
|
acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_interrupt *processor;
|
|
|
|
processor = (struct acpi_madt_generic_interrupt *)header;
|
|
if (BAD_MADT_GICC_ENTRY(processor, end))
|
|
return -EINVAL;
|
|
|
|
acpi_table_print_madt_entry(header);
|
|
|
|
acpi_map_gic_cpu_interface(processor);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define acpi_table_parse_madt(...) do { } while (0)
|
|
#endif
|
|
|
|
/*
|
|
* Enumerate the possible CPU set from the device tree and build the
|
|
* cpu logical map array containing MPIDR values related to logical
|
|
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
|
|
*/
|
|
static void __init of_parse_and_init_cpus(void)
|
|
{
|
|
struct device_node *dn = NULL;
|
|
|
|
while ((dn = of_find_node_by_type(dn, "cpu"))) {
|
|
u64 hwid = of_get_cpu_mpidr(dn);
|
|
|
|
if (hwid == INVALID_HWID)
|
|
goto next;
|
|
|
|
if (is_mpidr_duplicate(cpu_count, hwid)) {
|
|
pr_err("%s: duplicate cpu reg properties in the DT\n",
|
|
dn->full_name);
|
|
goto next;
|
|
}
|
|
|
|
/*
|
|
* The numbering scheme requires that the boot CPU
|
|
* must be assigned logical id 0. Record it so that
|
|
* the logical map built from DT is validated and can
|
|
* be used.
|
|
*/
|
|
if (hwid == cpu_logical_map(0)) {
|
|
if (bootcpu_valid) {
|
|
pr_err("%s: duplicate boot cpu reg property in DT\n",
|
|
dn->full_name);
|
|
goto next;
|
|
}
|
|
|
|
bootcpu_valid = true;
|
|
|
|
/*
|
|
* cpu_logical_map has already been
|
|
* initialized and the boot cpu doesn't need
|
|
* the enable-method so continue without
|
|
* incrementing cpu.
|
|
*/
|
|
continue;
|
|
}
|
|
|
|
if (cpu_count >= NR_CPUS)
|
|
goto next;
|
|
|
|
pr_debug("cpu logical map 0x%llx\n", hwid);
|
|
cpu_logical_map(cpu_count) = hwid;
|
|
next:
|
|
cpu_count++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Enumerate the possible CPU set from the device tree or ACPI and build the
|
|
* cpu logical map array containing MPIDR values related to logical
|
|
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
|
|
*/
|
|
void __init smp_init_cpus(void)
|
|
{
|
|
int i;
|
|
|
|
if (acpi_disabled)
|
|
of_parse_and_init_cpus();
|
|
else
|
|
/*
|
|
* do a walk of MADT to determine how many CPUs
|
|
* we have including disabled CPUs, and get information
|
|
* we need for SMP init
|
|
*/
|
|
acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
|
|
acpi_parse_gic_cpu_interface, 0);
|
|
|
|
if (cpu_count > NR_CPUS)
|
|
pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n",
|
|
cpu_count, NR_CPUS);
|
|
|
|
if (!bootcpu_valid) {
|
|
pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* We need to set the cpu_logical_map entries before enabling
|
|
* the cpus so that cpu processor description entries (DT cpu nodes
|
|
* and ACPI MADT entries) can be retrieved by matching the cpu hwid
|
|
* with entries in cpu_logical_map while initializing the cpus.
|
|
* If the cpu set-up fails, invalidate the cpu_logical_map entry.
|
|
*/
|
|
for (i = 1; i < NR_CPUS; i++) {
|
|
if (cpu_logical_map(i) != INVALID_HWID) {
|
|
if (smp_cpu_setup(i))
|
|
cpu_logical_map(i) = INVALID_HWID;
|
|
}
|
|
}
|
|
}
|
|
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
int err;
|
|
unsigned int cpu, ncores = num_possible_cpus();
|
|
|
|
init_cpu_topology();
|
|
|
|
smp_store_cpu_info(smp_processor_id());
|
|
|
|
/*
|
|
* are we trying to boot more cores than exist?
|
|
*/
|
|
if (max_cpus > ncores)
|
|
max_cpus = ncores;
|
|
|
|
/* Don't bother if we're effectively UP */
|
|
if (max_cpus <= 1)
|
|
return;
|
|
|
|
/*
|
|
* Initialise the present map (which describes the set of CPUs
|
|
* actually populated at the present time) and release the
|
|
* secondaries from the bootloader.
|
|
*
|
|
* Make sure we online at most (max_cpus - 1) additional CPUs.
|
|
*/
|
|
max_cpus--;
|
|
for_each_possible_cpu(cpu) {
|
|
if (max_cpus == 0)
|
|
break;
|
|
|
|
if (cpu == smp_processor_id())
|
|
continue;
|
|
|
|
if (!cpu_ops[cpu])
|
|
continue;
|
|
|
|
err = cpu_ops[cpu]->cpu_prepare(cpu);
|
|
if (err)
|
|
continue;
|
|
|
|
set_cpu_present(cpu, true);
|
|
max_cpus--;
|
|
}
|
|
}
|
|
|
|
void (*__smp_cross_call)(const struct cpumask *, unsigned int);
|
|
|
|
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
|
|
{
|
|
__smp_cross_call = fn;
|
|
}
|
|
|
|
static const char *ipi_types[NR_IPI] __tracepoint_string = {
|
|
#define S(x,s) [x] = s
|
|
S(IPI_RESCHEDULE, "Rescheduling interrupts"),
|
|
S(IPI_CALL_FUNC, "Function call interrupts"),
|
|
S(IPI_CPU_STOP, "CPU stop interrupts"),
|
|
S(IPI_TIMER, "Timer broadcast interrupts"),
|
|
S(IPI_IRQ_WORK, "IRQ work interrupts"),
|
|
S(IPI_WAKEUP, "CPU wake-up interrupts"),
|
|
};
|
|
|
|
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
|
|
{
|
|
trace_ipi_raise(target, ipi_types[ipinr]);
|
|
__smp_cross_call(target, ipinr);
|
|
}
|
|
|
|
void show_ipi_list(struct seq_file *p, int prec)
|
|
{
|
|
unsigned int cpu, i;
|
|
|
|
for (i = 0; i < NR_IPI; i++) {
|
|
seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
|
|
prec >= 4 ? " " : "");
|
|
for_each_online_cpu(cpu)
|
|
seq_printf(p, "%10u ",
|
|
__get_irq_stat(cpu, ipi_irqs[i]));
|
|
seq_printf(p, " %s\n", ipi_types[i]);
|
|
}
|
|
}
|
|
|
|
u64 smp_irq_stat_cpu(unsigned int cpu)
|
|
{
|
|
u64 sum = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < NR_IPI; i++)
|
|
sum += __get_irq_stat(cpu, ipi_irqs[i]);
|
|
|
|
return sum;
|
|
}
|
|
|
|
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
|
{
|
|
smp_cross_call(mask, IPI_CALL_FUNC);
|
|
}
|
|
|
|
void arch_send_call_function_single_ipi(int cpu)
|
|
{
|
|
smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
|
|
}
|
|
|
|
#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
|
|
void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
|
|
{
|
|
smp_cross_call(mask, IPI_WAKEUP);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
void arch_irq_work_raise(void)
|
|
{
|
|
if (__smp_cross_call)
|
|
smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
|
|
}
|
|
#endif
|
|
|
|
static DEFINE_RAW_SPINLOCK(stop_lock);
|
|
|
|
/*
|
|
* ipi_cpu_stop - handle IPI from smp_send_stop()
|
|
*/
|
|
static void ipi_cpu_stop(unsigned int cpu)
|
|
{
|
|
if (system_state == SYSTEM_BOOTING ||
|
|
system_state == SYSTEM_RUNNING) {
|
|
raw_spin_lock(&stop_lock);
|
|
pr_crit("CPU%u: stopping\n", cpu);
|
|
dump_stack();
|
|
raw_spin_unlock(&stop_lock);
|
|
}
|
|
|
|
set_cpu_online(cpu, false);
|
|
|
|
local_irq_disable();
|
|
|
|
while (1)
|
|
cpu_relax();
|
|
}
|
|
|
|
/*
|
|
* Main handler for inter-processor interrupts
|
|
*/
|
|
void handle_IPI(int ipinr, struct pt_regs *regs)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
|
|
if ((unsigned)ipinr < NR_IPI) {
|
|
trace_ipi_entry_rcuidle(ipi_types[ipinr]);
|
|
__inc_irq_stat(cpu, ipi_irqs[ipinr]);
|
|
}
|
|
|
|
switch (ipinr) {
|
|
case IPI_RESCHEDULE:
|
|
scheduler_ipi();
|
|
break;
|
|
|
|
case IPI_CALL_FUNC:
|
|
irq_enter();
|
|
generic_smp_call_function_interrupt();
|
|
irq_exit();
|
|
break;
|
|
|
|
case IPI_CPU_STOP:
|
|
irq_enter();
|
|
ipi_cpu_stop(cpu);
|
|
irq_exit();
|
|
break;
|
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
case IPI_TIMER:
|
|
irq_enter();
|
|
tick_receive_broadcast();
|
|
irq_exit();
|
|
break;
|
|
#endif
|
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
case IPI_IRQ_WORK:
|
|
irq_enter();
|
|
irq_work_run();
|
|
irq_exit();
|
|
break;
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
|
|
case IPI_WAKEUP:
|
|
WARN_ONCE(!acpi_parking_protocol_valid(cpu),
|
|
"CPU%u: Wake-up IPI outside the ACPI parking protocol\n",
|
|
cpu);
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
|
|
break;
|
|
}
|
|
|
|
if ((unsigned)ipinr < NR_IPI)
|
|
trace_ipi_exit_rcuidle(ipi_types[ipinr]);
|
|
set_irq_regs(old_regs);
|
|
}
|
|
|
|
void smp_send_reschedule(int cpu)
|
|
{
|
|
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
|
|
}
|
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
void tick_broadcast(const struct cpumask *mask)
|
|
{
|
|
smp_cross_call(mask, IPI_TIMER);
|
|
}
|
|
#endif
|
|
|
|
void smp_send_stop(void)
|
|
{
|
|
unsigned long timeout;
|
|
|
|
if (num_online_cpus() > 1) {
|
|
cpumask_t mask;
|
|
|
|
cpumask_copy(&mask, cpu_online_mask);
|
|
cpumask_clear_cpu(smp_processor_id(), &mask);
|
|
|
|
smp_cross_call(&mask, IPI_CPU_STOP);
|
|
}
|
|
|
|
/* Wait up to one second for other CPUs to stop */
|
|
timeout = USEC_PER_SEC;
|
|
while (num_online_cpus() > 1 && timeout--)
|
|
udelay(1);
|
|
|
|
if (num_online_cpus() > 1)
|
|
pr_warning("SMP: failed to stop secondary CPUs\n");
|
|
}
|
|
|
|
/*
|
|
* not supported here
|
|
*/
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
{
|
|
return -EINVAL;
|
|
}
|