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The TWD and SCU configs are selected by default as long as MSM_SCORPIONMP is false and/or MCT is false. Implementing the logic this way certainly saves lines in the Kconfig but it precludes those machines which select MSM_SCORPIONMP or MCT from participating in the single zImage effort because when those machines are combined with other SMP capable machines the TWD and SCU are no longer selected by default. Push the select out to the machine entries so that we can compile these machines together and still select the appropriate configs. Cc: Barry Song <baohua.song@csr.com> Acked-by: David Brown <davidb@codeaurora.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Simon Horman <horms@verge.net.au> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
51 lines
995 B
Plaintext
51 lines
995 B
Plaintext
config ARCH_SIRF
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bool "CSR SiRF" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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select MIGHT_HAVE_CACHE_L2X0
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select NO_IOPORT
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select PINCTRL
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select PINCTRL_SIRF
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help
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Support for CSR SiRFprimaII/Marco/Polo platforms
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if ARCH_SIRF
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menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
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config ARCH_ATLAS6
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bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
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default y
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select CPU_V7
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select SIRF_IRQ
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_PRIMA2
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bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
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default y
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select CPU_V7
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select SIRF_IRQ
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select ZONE_DMA
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_MARCO
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bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
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default y
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select ARM_GIC
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select CPU_V7
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select HAVE_ARM_SCU if SMP
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select HAVE_SMP
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select SMP_ON_UP
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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endmenu
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config SIRF_IRQ
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bool
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endif
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