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b89f311d7e
* Support for time namespaces in the VDSO, along with some associated cleanups. * Support for building rv32 randconfigs. * Improvements to the XIP port that allow larger kernels to function * Various device tree cleanups for both the SiFive and Microchip boards * A handful of defconfig updates, including enabling Nouveau. There are also various small cleanups. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmGN9T4THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiQEBD/9EvGe5jPb8binNiLN81ExYh3HGBJ9A sY+/rhVWnTUX/igBU4M9gNHu5Rts2ITlsBda9YnYRgMunAS1cnZJ/jbvckfsFA+s svehPgDZSR+BqBnVDN1hEsY+TrNbFFFZIApGDbImuC5+81np/p3u1zkl3hhO0amJ 7T46qxRq4iazbuohi47/ba6ufXyLb8XBg3LTUfp+lTnH7/VLbwspPWdzNgiJpMzB qEWfYd4au2zfqHC6SYHXidy/tkquhJ6DgKq0G3+XUCugeennMeisDWI9GsxTAzIa Pynm9GHA/AuK1/kt9qB/Czsg7bqY8RUreUMLNZEyHzwKA1OWQVxlfCdl5zIpxlkq eJkxjbhhPuneVRGUSJgKQqBEUtGlH9yISqO2CFFdKRqzm1ImJtkAJGC+SubpKSbU D+ZAGbAyEwDUfl1yyKzKRg6YnzntMxh8sfNdJRYMrOhczk8L//R8yxG6SX6bjw7W lTQk7wkpo2yS7L799dukKdlllYbUvqavZwsIHTyb1TsRoavQeqoJq/6jKXJNhFHD rA/OQgCUXuHTmpgdDUhHuLZVvJqT5n8Vxigi30nIq24KOgTom8tRRtiAWOJv7G+Z b/Y3eq0VE8yjhPSbtsAxooZnpEVgXsVqx3t/lBt0MiJE1a3JLSSchRTHBjWllCiV +yvCerCh8PoT8w== =Mpen -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for time namespaces in the VDSO, along with some associated cleanups. - Support for building rv32 randconfigs. - Improvements to the XIP port that allow larger kernels to function - Various device tree cleanups for both the SiFive and Microchip boards - A handful of defconfig updates, including enabling Nouveau. There are also various small cleanups. * tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: defconfig: enable DRM_NOUVEAU riscv/vdso: Drop unneeded part due to merge issue riscv: remove .text section size limitation for XIP riscv: dts: sifive: add missing compatible for plic riscv: dts: microchip: add missing compatibles for clint and plic riscv: dts: sifive: drop duplicated nodes and properties in sifive riscv: dts: sifive: fix Unleashed board compatible riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible riscv: dts: microchip: use vendor compatible for Cadence SD4HC riscv: dts: microchip: drop unused pinctrl-names riscv: dts: microchip: drop duplicated MMC/SDHC node riscv: dts: microchip: fix board compatible riscv: dts: microchip: drop duplicated nodes dt-bindings: mmc: cdns: document Microchip MPFS MMC/SDHCI controller riscv: add rv32 and rv64 randconfig build targets riscv: mm: don't advertise 1 num_asid for 0 asid bits riscv: set default pm_power_off to NULL riscv/vdso: Add support for time namespaces
149 lines
4.1 KiB
Makefile
149 lines
4.1 KiB
Makefile
# This file is included by the global makefile so that you can add your own
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# architecture-specific flags and dependencies.
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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OBJCOPYFLAGS := -O binary
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LDFLAGS_vmlinux :=
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ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
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LDFLAGS_vmlinux := --no-relax
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KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
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CC_FLAGS_FTRACE := -fpatchable-function-entry=8
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endif
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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KBUILD_CFLAGS_MODULE += -mcmodel=medany
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endif
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export BITS
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ifeq ($(CONFIG_ARCH_RV64I),y)
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BITS := 64
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UTS_MACHINE := riscv64
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KBUILD_CFLAGS += -mabi=lp64
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KBUILD_AFLAGS += -mabi=lp64
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KBUILD_LDFLAGS += -melf64lriscv
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else
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BITS := 32
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UTS_MACHINE := riscv32
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KBUILD_CFLAGS += -mabi=ilp32
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KBUILD_AFLAGS += -mabi=ilp32
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KBUILD_LDFLAGS += -melf32lriscv
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endif
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ifeq ($(CONFIG_LD_IS_LLD),y)
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KBUILD_CFLAGS += -mno-relax
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KBUILD_AFLAGS += -mno-relax
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ifndef CONFIG_AS_IS_LLVM
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KBUILD_CFLAGS += -Wa,-mno-relax
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KBUILD_AFLAGS += -Wa,-mno-relax
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endif
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endif
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# ISA string setting
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riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
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riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
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riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
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riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
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KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
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KBUILD_AFLAGS += -march=$(riscv-march-y)
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KBUILD_CFLAGS += -mno-save-restore
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KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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KBUILD_CFLAGS += -mcmodel=medlow
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endif
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ifeq ($(CONFIG_CMODEL_MEDANY),y)
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KBUILD_CFLAGS += -mcmodel=medany
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endif
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ifeq ($(CONFIG_PERF_EVENTS),y)
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KBUILD_CFLAGS += -fno-omit-frame-pointer
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endif
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KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax)
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# GCC versions that support the "-mstrict-align" option default to allowing
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# unaligned accesses. While unaligned accesses are explicitly allowed in the
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# RISC-V ISA, they're emulated by machine mode traps on all extant
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# architectures. It's faster to have GCC emit only aligned accesses.
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KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
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ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
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prepare: stack_protector_prepare
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stack_protector_prepare: prepare0
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$(eval KBUILD_CFLAGS += -mstack-protector-guard=tls \
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-mstack-protector-guard-reg=tp \
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-mstack-protector-guard-offset=$(shell \
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awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}' \
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include/generated/asm-offsets.h))
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endif
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# arch specific predefines for sparse
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CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS)
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# Default target when executing plain make
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boot := arch/riscv/boot
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ifeq ($(CONFIG_XIP_KERNEL),y)
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KBUILD_IMAGE := $(boot)/xipImage
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else
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KBUILD_IMAGE := $(boot)/Image.gz
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endif
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head-y := arch/riscv/kernel/head.o
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core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
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core-$(CONFIG_KVM) += arch/riscv/kvm/
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libs-y += arch/riscv/lib/
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libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
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PHONY += vdso_install
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vdso_install:
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
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ifeq ($(CONFIG_MMU),y)
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prepare: vdso_prepare
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vdso_prepare: prepare0
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso include/generated/vdso-offsets.h
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endif
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ifneq ($(CONFIG_XIP_KERNEL),y)
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ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
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KBUILD_IMAGE := $(boot)/loader.bin
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else
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KBUILD_IMAGE := $(boot)/Image.gz
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endif
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endif
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BOOT_TARGETS := Image Image.gz loader loader.bin xipImage
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all: $(notdir $(KBUILD_IMAGE))
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$(BOOT_TARGETS): vmlinux
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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@$(kecho) ' Kernel: $(boot)/$@ is ready'
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Image.%: Image
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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install: install-image = Image
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zinstall: install-image = Image.gz
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install zinstall:
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$(CONFIG_SHELL) $(srctree)/$(boot)/install.sh $(KERNELRELEASE) \
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$(boot)/$(install-image) System.map "$(INSTALL_PATH)"
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PHONY += rv32_randconfig
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rv32_randconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/32-bit.config \
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-f $(srctree)/Makefile randconfig
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PHONY += rv64_randconfig
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rv64_randconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/64-bit.config \
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-f $(srctree)/Makefile randconfig
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