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50f5bd5718
As we are about to access the APRs from the GICv2 uaccess interface, make this logic generally available. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>
315 lines
8.1 KiB
C
315 lines
8.1 KiB
C
/*
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* VGIC system registers handling functions for AArch64 mode
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include "vgic.h"
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#include "sys_regs.h"
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static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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u32 host_pri_bits, host_id_bits, host_seis, host_a3v, seis, a3v;
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struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_vmcr vmcr;
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u64 val;
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vgic_get_vmcr(vcpu, &vmcr);
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if (p->is_write) {
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val = p->regval;
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/*
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* Disallow restoring VM state if not supported by this
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* hardware.
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*/
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host_pri_bits = ((val & ICC_CTLR_EL1_PRI_BITS_MASK) >>
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ICC_CTLR_EL1_PRI_BITS_SHIFT) + 1;
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if (host_pri_bits > vgic_v3_cpu->num_pri_bits)
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return false;
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vgic_v3_cpu->num_pri_bits = host_pri_bits;
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host_id_bits = (val & ICC_CTLR_EL1_ID_BITS_MASK) >>
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ICC_CTLR_EL1_ID_BITS_SHIFT;
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if (host_id_bits > vgic_v3_cpu->num_id_bits)
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return false;
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vgic_v3_cpu->num_id_bits = host_id_bits;
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host_seis = ((kvm_vgic_global_state.ich_vtr_el2 &
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ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT);
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seis = (val & ICC_CTLR_EL1_SEIS_MASK) >>
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ICC_CTLR_EL1_SEIS_SHIFT;
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if (host_seis != seis)
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return false;
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host_a3v = ((kvm_vgic_global_state.ich_vtr_el2 &
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ICH_VTR_A3V_MASK) >> ICH_VTR_A3V_SHIFT);
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a3v = (val & ICC_CTLR_EL1_A3V_MASK) >> ICC_CTLR_EL1_A3V_SHIFT;
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if (host_a3v != a3v)
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return false;
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/*
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* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
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* The vgic_set_vmcr() will convert to ICH_VMCR layout.
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*/
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vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
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vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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val = 0;
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val |= (vgic_v3_cpu->num_pri_bits - 1) <<
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ICC_CTLR_EL1_PRI_BITS_SHIFT;
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val |= vgic_v3_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT;
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val |= ((kvm_vgic_global_state.ich_vtr_el2 &
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ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT) <<
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ICC_CTLR_EL1_SEIS_SHIFT;
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val |= ((kvm_vgic_global_state.ich_vtr_el2 &
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ICH_VTR_A3V_MASK) >> ICH_VTR_A3V_SHIFT) <<
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ICC_CTLR_EL1_A3V_SHIFT;
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/*
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* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
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* Extract it directly using ICC_CTLR_EL1 reg definitions.
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*/
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val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
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val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
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p->regval = val;
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}
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return true;
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}
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static bool access_gic_pmr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (p->is_write) {
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vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK;
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}
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return true;
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}
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static bool access_gic_bpr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (p->is_write) {
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vmcr.bpr = (p->regval & ICC_BPR0_EL1_MASK) >>
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ICC_BPR0_EL1_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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p->regval = (vmcr.bpr << ICC_BPR0_EL1_SHIFT) &
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ICC_BPR0_EL1_MASK;
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}
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return true;
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}
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static bool access_gic_bpr1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_vmcr vmcr;
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if (!p->is_write)
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p->regval = 0;
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vgic_get_vmcr(vcpu, &vmcr);
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if (!vmcr.cbpr) {
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if (p->is_write) {
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vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
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ICC_BPR1_EL1_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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p->regval = (vmcr.abpr << ICC_BPR1_EL1_SHIFT) &
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ICC_BPR1_EL1_MASK;
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}
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} else {
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if (!p->is_write)
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p->regval = min((vmcr.bpr + 1), 7U);
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}
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return true;
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}
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static bool access_gic_grpen0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (p->is_write) {
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vmcr.grpen0 = (p->regval & ICC_IGRPEN0_EL1_MASK) >>
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ICC_IGRPEN0_EL1_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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p->regval = (vmcr.grpen0 << ICC_IGRPEN0_EL1_SHIFT) &
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ICC_IGRPEN0_EL1_MASK;
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}
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return true;
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}
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static bool access_gic_grpen1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (p->is_write) {
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vmcr.grpen1 = (p->regval & ICC_IGRPEN1_EL1_MASK) >>
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ICC_IGRPEN1_EL1_SHIFT;
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vgic_set_vmcr(vcpu, &vmcr);
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} else {
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p->regval = (vmcr.grpen1 << ICC_IGRPEN1_EL1_SHIFT) &
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ICC_IGRPEN1_EL1_MASK;
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}
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return true;
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}
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static void vgic_v3_access_apr_reg(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p, u8 apr, u8 idx)
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{
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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uint32_t *ap_reg;
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if (apr)
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ap_reg = &vgicv3->vgic_ap1r[idx];
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else
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ap_reg = &vgicv3->vgic_ap0r[idx];
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if (p->is_write)
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*ap_reg = p->regval;
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else
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p->regval = *ap_reg;
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}
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static bool access_gic_aprn(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r, u8 apr)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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goto err;
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vgic_v3_access_apr_reg(vcpu, p, apr, idx);
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return true;
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err:
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if (!p->is_write)
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p->regval = 0;
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return false;
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}
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static bool access_gic_ap0r(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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return access_gic_aprn(vcpu, p, r, 0);
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}
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static bool access_gic_ap1r(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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return access_gic_aprn(vcpu, p, r, 1);
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}
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static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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/* Validate SRE bit */
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if (p->is_write) {
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if (!(p->regval & ICC_SRE_EL1_SRE))
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return false;
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} else {
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p->regval = vgicv3->vgic_sre;
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}
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return true;
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}
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static const struct sys_reg_desc gic_v3_icc_reg_descs[] = {
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{ SYS_DESC(SYS_ICC_PMR_EL1), access_gic_pmr },
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{ SYS_DESC(SYS_ICC_BPR0_EL1), access_gic_bpr0 },
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{ SYS_DESC(SYS_ICC_AP0R0_EL1), access_gic_ap0r },
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{ SYS_DESC(SYS_ICC_AP0R1_EL1), access_gic_ap0r },
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{ SYS_DESC(SYS_ICC_AP0R2_EL1), access_gic_ap0r },
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{ SYS_DESC(SYS_ICC_AP0R3_EL1), access_gic_ap0r },
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{ SYS_DESC(SYS_ICC_AP1R0_EL1), access_gic_ap1r },
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{ SYS_DESC(SYS_ICC_AP1R1_EL1), access_gic_ap1r },
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{ SYS_DESC(SYS_ICC_AP1R2_EL1), access_gic_ap1r },
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{ SYS_DESC(SYS_ICC_AP1R3_EL1), access_gic_ap1r },
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{ SYS_DESC(SYS_ICC_BPR1_EL1), access_gic_bpr1 },
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{ SYS_DESC(SYS_ICC_CTLR_EL1), access_gic_ctlr },
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{ SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
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{ SYS_DESC(SYS_ICC_IGRPEN0_EL1), access_gic_grpen0 },
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{ SYS_DESC(SYS_ICC_IGRPEN1_EL1), access_gic_grpen1 },
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};
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int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
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u64 *reg)
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{
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struct sys_reg_params params;
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u64 sysreg = (id & KVM_DEV_ARM_VGIC_SYSREG_MASK) | KVM_REG_SIZE_U64;
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params.regval = *reg;
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params.is_write = is_write;
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params.is_aarch32 = false;
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params.is_32bit = false;
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if (find_reg_by_id(sysreg, ¶ms, gic_v3_icc_reg_descs,
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ARRAY_SIZE(gic_v3_icc_reg_descs)))
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return 0;
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return -ENXIO;
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}
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int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id,
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u64 *reg)
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{
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struct sys_reg_params params;
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const struct sys_reg_desc *r;
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u64 sysreg = (id & KVM_DEV_ARM_VGIC_SYSREG_MASK) | KVM_REG_SIZE_U64;
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if (is_write)
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params.regval = *reg;
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params.is_write = is_write;
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params.is_aarch32 = false;
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params.is_32bit = false;
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r = find_reg_by_id(sysreg, ¶ms, gic_v3_icc_reg_descs,
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ARRAY_SIZE(gic_v3_icc_reg_descs));
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if (!r)
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return -ENXIO;
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if (!r->access(vcpu, ¶ms, r))
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return -EINVAL;
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if (!is_write)
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*reg = params.regval;
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return 0;
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}
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